Ap7000 BusSpeed and their divisions

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Hi..
I have some question that weren't answered in the datasheet so far:

a) What is the maximum allowed clock for PBA
b) What is the maximum allowed clock for PBB

-> There is a propsal that PBA is divided by 4 and PBB is divied by 2 (in relation to the CPU-clock)

c) Is this a MUST for stable operation?

I need to maximize PBA-Throughput at any time, but due to the lack of information, i didnt managed that until now. I use CUP/2=PBB and CPU/4=PBA everytime. Except in Sleepmode where everything is clocked at Crystal-original-clock

has anyone more information?

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:( *push* :-(

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Hello,
data sheet gives you 150MHz for CPU and in chapter 10.5.4 it says any speed as long as CPU >= HSB >= PBA. Therefore I think PBA should be able to run 150MHz too.
At the other side we had problems when we let PBA run at CPU speed.

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Quote:
At the other side we had problems when we let PBA run at CPU speed.
Exactly.
But for this i have a reason: HSB maximum clock is CPU/2 du to this statement:
Quote:
The maximum frequenzy of the SDRAMC interface is the same as the max frequnzy for the
HSB
....
SDRAM Controller Clock Frequency = 1/(2Tcpu) MHz

But specifications for PBA or PBB are not given :-(

The Datasheet speaks of a standard division:

Quote:
These numbers are relative to the actual CPU clock frequency, using the standard bus divi-
sion: HSB and PBB divided by two. PBA divided by four.

OR:
Note:1.The bus clocks in the system should be divided, relative to the CPU, to be sure they operate in their specified range. The
HSB and PBB bus clocks should be divided by two and the PBA bus clock should be divided by four relative to the CPU
clock. The division factor of the buses can be set by programming the Power Manager register CKSEL.

OR:
To ensure correct operation, frequencies must be selected so that fCPU ≥ fHSB ≥ fPBA,B. Also, fre-
quencies must never exceed the specified maximum frequency for each clock domain.


Specified range???
Specified maximum frequency for each clock domain???
;-)