Anyone got SAMD21/R21 SPI Hardware SS working with ASF?

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[since "ASF" is now "Atmel Software Framework" - not just AVR]

D21 ASF Manual: http://www.atmel.com/Images/Atme...

The one and only mention of master_slave_select_enable is in Table 14-3 - and all that tells you is that it's a bool, and the description is just "Enable Master Slave Select"

There is no explanation nor illustration of how to actually use that option!

:roll:

None of the examples uses it.

If I take the SAMD21 Xplained-Pro SPI_QUICK_START_MASTER_CALLBACK example and add the following:

config_spi_master.pinmux_pad1 = EXT1_SPI_SERCOM_PINMUX_PAD1;
config_spi_master.master_slave_select_enable = true;

the result is a mess - see the attached scope traces (showing SCK and SS).

The version with master_slave_select_enable set actually takes longer - and gets split up into individual bytes!

Anyone got this actually working :?:

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Several Cortex chips will have different behaviours:
1. shake SS on every transfer.
2. implement haywire-ability
3. raise SS at end of transfer
4. wake up a Slave.
5. ignore it completely.

I have no inclination to use any Atmel ARM chips. Nor read the manual.

IMHO, NXP seem to have the best arrangements.

I have no real experience with ASF. Only built Xmega examples. Then got totally lost in the minefield.

I find it easier to just write from the data sheet.

OTOH, TI, NXP, ST, Freescale have example code that is reasonably easy to follow. Generally using the "normal" SPI.

The Freescale hardware SS is really weird, but it works. You just need to try it out for yourself.

David.

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david.prentice wrote:
I find it easier to just write from the data sheet..

The D20/D21/R21 datasheets seems almost as impenetrable as the ASF code.

:?

Trouble is, they describe each duck individually - but there's no help whatsoever in how to get those ducks lined-up to make the thing work!

And, of course, all the examples are ASF.

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I know that this is an Atmel Forum.
I am very fond of the AVR8 chips for their versalility and ease of use.

OTOH, I can't see what the Atmel ARM chips offer to the rest of the world.
ST, NXP, TI, Freescale, ... all offer cheap evaluation hardware and good example code.

I suppose that I might look at an Atmel D21 board one day.

Sorry to be so negative. OTOH, SPI should be pretty straightforward. i.e. investigate it yourself with a Logic Analyser.

After all, a Master tends to blit out SPI at maximum speed. If your chip has FIFO or DMA, you can remove some of the CPU load. Ideally, it releases SS when complete.

David.

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TI don't have any Cortex-M0, and I think their M3s are all NRND?

david.prentice wrote:
cheap evaluation hardware

The Xplained-pro boards aren't exactly expensive.

Quote:
SPI should be pretty straightforward

Indeed it should!

Quote:
investigate it yourself with a Logic Analyser

Where do you think those scope traces came from?

8)

But I don't think customers should have to reverse-engineer this stuff!

:x

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Quote:

OTOH, I can't see what the Atmel ARM chips offer to the rest of the world.

Well in theory it looks like the main "sales item" is AS6 and ASF. The idea being that you could potentially write processor agnostic code using their cross platform drivers like GPIO, IOPORT or whatever it's called this week. You can learn about it on the Xmega you are familiar with then doing the LED flashing thing on AVR32-UC3 or SAM3/4/D20/D21 should be totally familiar. Similarly using GCC for all means that you are familiar with a common set of tools. If you want to place a section at a fixed address (section .foo) you do it the same whether it's avr-gcc, arm-gcc or avr32-gcc and so on.

Oh and there's even the fact that now, with Atmel-ICE, you can in theory do it all with the one debugger.

Those are the upsides.

The intense complexity of the multi-layered onion that is ASF is a definite downside. I've used USB libraries from MChip and NXP/CodeRed and found them easy to use (oh and, of course LUFA) while I'm befuddled by the same in ASF though I have no real desire to use Xmega or UC3 where they'd apply anyway (though once the M0/M3/M4 USB chips start to arrive I might get interested).

There's also the relative cost of their eval+debugger boards. They seem to be in a different realm to some of their competitors so they aren't "throw away" evaluation prices - you have to be pretty dedicated to commit. (I think I got boards from 3 other for the cost of 1 Atmel ARM board).

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@Andy,

I see that RS have got one D21 and 70 D20 boards in stock. I still don't see what Atmel have that is superior to other manufacturers.

The ST and Freescale boards can use Arduino shields. Which is handy for comparing different implementations.

Oh, I saw your scope traces. They made no sense at all. Now, a LA screenshot is a lot more useful. (to a distant reader)

David.

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david.prentice wrote:
I saw your scope traces. They made no sense at all.

As I said, they show SCK and SS.

Admitedly, I didn't say which was which!

It doesn't help that the forum shows them in reverse order.

So this is the trace of the unmodified Atmel ASF example, as supplied:

The upper trace is SCK; lower is SS.

So a nice "normal" SPI transaction: SS goes low; SCK clocks all the data; SS goes high again. It all takes 1.65ms

And this is the trace of the modified code, trying to use the hardware SS control:

this has a load of SCK "bursts", with SS separately asserted around each. It all takes 2.19ms

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clawson wrote:
once the M0/M3/M4 USB chips start to arrive I might get interested

The D21 & R21 have USB.

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clawson wrote:
The idea being that you could potentially write processor agnostic code using their cross platform drivers

So does anyone know if any other chips share the same SPI peripheral - and, if so, how to use the hardware SS on those :?:

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awneil wrote:

And this is the trace of the modified code, trying to use the hardware SS control:

this has a load of SCK "bursts", with SS separately asserted around each. It all takes 2.19ms

RTFM: This is the documented behaviour!

:shock:

So that's completely useless for any SPI device that I know of - including, in particular, Atmel's own AT86RF233 (which forms an integral part of the R21)

:roll:

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awneil wrote:
completely useless for any SPI device that I know of

And it doesn't even match Atmel's own description & illustration in the D21 (and R21) datasheet of how SPI normally works!

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awneil wrote:
So that's completely useless for any SPI device that I know of - including, in particular, Atmel's own AT86RF233 (which forms an integral part of the R21)

... and cue the saxophone ...

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From memory, other Cortex chips can do this. (or similar)

No, I can't think of any SPI hardware chips that would be happy with single SPI bytes.
However it would be ideal for a 74HC595 chip.

I am sure that the D21 has got some useful modes. I am too idle to read the Atmel docs. (There are plenty enough docs from NXP, Freescale, ST to read first!)

David.

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david.prentice wrote:
From memory, other Cortex chips can do this.

jharley on the other forum says that other Atmel chips do it:

http://www.at91.com/discussions/...

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