ADC reading erratically on ATMEGA 16

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Hello,
I'm using a single ended analog input on an ATMEGA16. When I read values from a battery, I get a fairly consistent jumping around of ADC readings. There are two types of variations which occur. I get a variation of 1 or 2 counts occasionally, and this is normal. But as frequently I get a variation of 9 or 10 counts. A recent set of readings was...
734
734
734
723
734
735
734
723
723
734
734
734

For any input voltage, the readings are correct about 60-70% of the time, and then about 30-40% they are low by a consistent amount. It's almost like I am losing a digit in the 10's place. Does anyone know why the ADC would be jumping around like that?

thanks

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It is interesting that all of the variation is downward, and quite self-consistent.

You might check that the sample rate is not too high or too low. This can particularly happen if the processor clock is not what you think it is.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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I should add that this phenomenon occurs at many sample rates. I have the ADC reading during the timer 0 interrupt subroutine. The overflow occurs at settings of 100ms, 500ms, 1 sec,... up to 1 hr. This behavior has been observed at sample rates as slow as 1 second.

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But, what is important is the ADC clock prescaler. What is your system clock and how do you have the prescaler set? The sample rate is not really relevant except in so far as it shows that you know what the system clock is.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Just to add onto Jim, your ADC clock should be between 200KHz and 50KHz, not faster, not slower. You can go a bit faster in 8Bit mode but it looks like you want the full 10 bit

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So, I've been running the adc at 1000 kHz. Is this likely to be a problem? And why?

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Well Mr. Nedward. I reduced the adc frequency from 1000 kHz to 125 kHz and the problem is gone. Thank you for the help. Would you mind explaining why the adc frequency must remain in the range given?

thanks

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The ADC works by sampling the input voltage onto a capacitor then ramping a DAC to generate a stepped voltage that is run through a comparator against the sample until it equals/exceeds the sample. That stepping requires a reasonable amount of time to stabilise for the comparison. This simply won't work if you run it too fast.

All this is explained (in better detail!) in the datasheet.

Because of the divisors available it can often help to slow the CPU down rather than speed it up so you can get closer to the 200Khz rate.

Say you use an 8MHz AVR then you can't use /32 as that is 250kHz - outside the acceptable range so you have to use /64 so that means you are limited to 125kHz. If the AVR was clocked at 6MHz then you could use /32 to get 187.5kHz. In fact best might be 6.4MHz which could get you to 200kHz.

Cliff

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As you point out, it is stated right in the datasheet, p 205, that 50kHz to 200kHz are used for maximum resolution of the adc. Thanks.