8 MegaByte SPI ram in 8 pins!

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Kartman
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Posted by Kartman: Mon. Jan 21, 2019 - 12:05 AM
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I stumbled across these devices last week when looking at some ESP32 boards. Yes, 8 whopping megabytes of pseudo-static ram in a little soic 8 package using SPI/QSPI for less than a USD.

 

https://www.electrodragon.com/pr...

 

Seems there's a few companies making these devices, but they seem to be obscure Chinese and Taiwanese companies. 

 

The ESP32 can map these devices into its memory map - unfortunately, most other micros can only use it as a spi peripheral - ie the 8MB of ram does not appear as 'normal' memory. 

 

[edit] I should note that my relationship with Electrodragon is purely as a satisfied customer and post the link as where to get these parts and for the link to the datasheet. The likes of Digikey and Mouser don't seem to stock these parts.

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Learning and Information, General Electronics, PIC32MZ1025DAG169, ATxmega128A1U
Last Edited: Mon. Jan 21, 2019 - 01:57 AM
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westfw
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Posted by westfw: Mon. Jan 21, 2019 - 02:52 AM
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The ESP32 can map these devices into its memory map - unfortunately, most other micros can only use it as a spi peripheral - ie the 8MB of ram does not appear as 'normal' memo

Are you sure?  A lot of "recent" chips support QSPI Flash, with run-in-place capability (you can run code direct from the SPI Flash - hopefully you have cache!)

I'm not sure whether they all support RAM, though.

 

For example, Adafruit put QSPI flash on all their "M4" boards that use the Atmel SAMD51 chips.  The SAMD51 has HW support for QSPI, separate from the SERCOM SPI ports...

 

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Kartman
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Posted by Kartman: Mon. Jan 21, 2019 - 04:26 AM
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I did a quick search last night for possible chips - most of the newer chips do XIP (execute in place) which works for serial flash chips but support for spi/qspi ram is indeed rare. There is mention of hyperbus devices, but support is minimal - Cypress seems to be the only one at the moment. I looked at the iMX RT1050 and the SAMD51 series. They'll do the XIP, but I couldn't see anything to suggest they'll do ram. I'm open to correction here. 

 

So it looks like the Chinese have made their own move and decided on spi/qspi. Nevertheless where you have apps with secondary data where the indirect access isn't necessarily a major performance hit, then these devices are a possible solution. Even as a large queue where you need to grab a lot of data then write it off at a slower pace to flash or sdcard.

 

I think my LSI 11/23 might be getting a ram upgrade soon!

 

 

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joeymorin
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Posted by joeymorin: Mon. Jan 21, 2019 - 05:10 PM
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Thanks for this. I've got a couple of ideas already :-)

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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ka7ehk
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Posted by ka7ehk: Mon. Jan 21, 2019 - 05:56 PM
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Max frequency of 104MHz? Woweee! Maybe this is bits per second with QPI? Even so, that would be 26MHz clock rate! I see max clock up to 84MHz!

 

OEM appears to be here: http://ipusltd.com/Products_en.h... also sramsun.

 

The "datasheet" links (on the ipsltd page) are really mailto links - apparently, you have to request the data sheet. Data sheets have been requested though there is a datasheet (from sramsun) in English linked on the ElectroDragon page. I want to know the current consumption!  64Mbit device read/write current is TBD; standby is 180uA.

 

16Mbit, 32Mbit, 64Mbit versions. It appears to be a sort of DRAM with built-in refresh.

 

Think of what this can do for over-the-air (wireless) firmware updates. The candidate firmware can be loaded into this thingie, analysis can be done on CRC and security all before it even enters the MCU. Maybe even unpack it from transport encoding into a boot image, again, without entering the MCU. Then, once validated and/or translated, a bootloader can transfer code from said thingie into the chip.

 

I want, I want!

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Mon. Jan 21, 2019 - 06:23 PM
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Kartman
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Posted by Kartman: Mon. Jan 21, 2019 - 09:17 PM
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Its 104MHz times four bits. The actual data rate isn’t that rosy - there’s wait states and other caveats.

As for firmware updates, i’ve used serial flash for this in the past. You usually have enough space to keep an old copy as well so you can rewind the update.

Other manufacturers are Lyontech and apmemory.
http://www.lyontek.com.tw/en/ddropiram.html
http://www.apmemory.com/html/product_psram.php

I too want to know the power consumption. I’ve piggybacked a chip onto my esp32 thing board but measuring the current might be a bit trickier.

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westfw
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Posted by westfw: Mon. Jan 21, 2019 - 11:03 PM
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Can you use them to make a "LogicShrimp"-like logic analyzer?

 

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Kartman
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Posted by Kartman: Mon. Jan 21, 2019 - 11:50 PM
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The possibility is there. You just need to ensure you let the device refresh itself at regular intervals - this means you can't keep CS low too long.

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Paulvdh
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Posted by Paulvdh: Tue. Jan 22, 2019 - 01:22 AM
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"LogicShrimp" rang a bell, so I followed the link to Dangerous Prototypes.

Then I thought that all such hardware is useless without good software.

The best (open source) software I know is Sigrok, and it seems to support the Logic Shrimp:

https://sigrok.org/wiki/Logic_Shrimp

 

However, the logic shrimp looks like a oudated and archaic platform.

The defacto default for beginners with Sigrok are the "24Mhz 8ch" boxes from China with a Cypress Cy7 something 68013...

These can live stream 24Msps at 8 channels to your PC.

The logic shrimp is however limited to 20Msps and 4 channels, and to the buffer size of the chips used.

 

If you need more performance from a logic analyser a much more logical path is to use one of the many existing boards with a microntroller, an FPGA and some beefy RAM chip for buffering.

It seems unlikely that a "logic shrimp" like analyser is going to be better than the FPGA + RAM boards.

I have some vage memories (Hackaday?) of a project that re purposed a PC DDR Ram board for a logic analyser.

I also remember something about using Dynamic ram with an AVR. It needed about 10% of the CPU cycles to refresh the RAM.

 

I am sort of wondering now what a microcontroller with 8MByte of built in RAM would cost nowaday's.

Doing magic with a USD 7 Logic Analyser: https://www.avrfreaks.net/comment/2421756#comment-2421756

Bunch of old projects with AVR's: http://www.hoevendesign.com

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ka7ehk
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Posted by ka7ehk: Tue. Jan 22, 2019 - 01:24 AM
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Is DRAM technology compatible with standard CMOS?

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Kartman
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Posted by Kartman: Tue. Jan 22, 2019 - 01:42 AM
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ka7ehk wrote:
Is DRAM technology compatible with standard CMOS?

 

It is standard CMOS!

 

The beauty of this little device is you get the density of dram, but the evil of refresh is taken care of internally. The catch is that you can only keep CS low for up to 8us. Keep it low too long and refreshes get missed and your data may go west.  So you really want the SPI speed to be as high as you can get it. This means you can probably only read or write a couple of bytes with an AVR at 16MHz.

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gchapman
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Posted by gchapman: Tue. Jan 22, 2019 - 02:28 AM (Reply to #9)
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Paulvdh wrote:
If you need more performance from a logic analyser a much more logical path is to use one of the many existing boards with a microntroller, an FPGA and some beefy RAM chip for buffering.
or an MPU with specific glue logic and a fair amount of RAM :

CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit

Paulvdh wrote:
I also remember something about using Dynamic ram with an AVR.
XMEGA A1U has a SDRAM controller.

The Atmel XMEGA128A1 board had SDRAM; the Microchip XMEGA128A1U board has external SRAM.

Paulvdh wrote:
I am sort of wondering now what a microcontroller with 8MByte of built in RAM would cost nowaday's.
10.24USD each for 5000 of a 32MB PIC32MZ DA (11.82USD each for 100)

Posts 2 and 3 in HUGE Memory MCU | AVR Freaks show competition from Allwinner and Renesas (IIRC, the world's largest manufacturer of MCUs)

 

Cypress SuperSpeed Explorer Kit as a Logic Analyzer

https://sysprogs.com/w/tag/analyzer2go/

http://web.archive.org/web/20150407022557/http://www.atmel.com/tools/XMEGA-A1XPLAINED.aspx

XMEGA A1U Xplained Pro Evaluation Kit

AN_8058 AVR1312: Using the XMEGA External Bus Interface (PDF page 7 for start of SDRAM information)

via ATxmega128A1U - 8-bit AVR Microcontrollers - Microcontrollers and Processors - Microcontrollers and Processors

PIC32MZ1025DAG169 - 32-bit PIC Microcontrollers - Microcontrollers and Processors - Microcontrollers and Processors

https://www.microchipdirect.com/product/search/all/PIC32MZ1025DAG169

 

edit: AVR1312

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Tue. Jan 22, 2019 - 02:43 AM
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ka7ehk
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Posted by ka7ehk: Tue. Jan 22, 2019 - 06:19 AM
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Just got a confidential (!) spec sheet from IPUS Ltd. This is one of the OEMs for the 16 MBit, 32Mbit, and 64Mbit ram chips referenced in the first message.

 

Maximum Read/write current is 10mA at 64Mbit. A clock rate is not given.

 

Following all refers to 64Mbit. Could not find any limitations on max time between chip selects. There is a min time (18ns) but no max. MAX select duration is 8uS. SPI read takes 52 clocks. To do that in 8uS means 0.15uS max clock period or 6.7MHz MINIMUM clock rate for a read. With care, you could JUST do it with a 16MHz MCU unless there is a PLL clock for SPI.

 

jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Kartman
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Posted by Kartman: Tue. Jan 22, 2019 - 06:55 AM
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Thanks for the info Jim. I dare say you won't use a coin cell to back these babies up.  

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Paulvdh
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Posted by Paulvdh: Tue. Jan 22, 2019 - 08:47 AM
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A link to a preleminary datasheet of this chip was not hard to find:
https://drive.google.com/file/d/1-5NtY1bz0l9eYN9U0U4dP3uASwnMmYGP/view

 

And although it seems to be a cool chip, I'm not sure what I would use it for.

For "large" applications I would probably prefer a chip with built in or direct support for Dram.

For logging applications low power and data retention are often important factors.

 

Tnx Chapman for the FX3 link. It seemst there has already been some work done to get the FX3 board compatible with Sigrok.

https://github.com/cnlohr/fx3fun

 

Terribly unrelated, but impressive none-the-less is other stuff on the sysprogs website.

With the Segger J-link they can capture trace debug data to backtrack & analyse through uC past instructions:

https://sysprogs.com/w/announcing-visualgdb-5-4-preview-3-with-j-trace-support/

Doing magic with a USD 7 Logic Analyser: https://www.avrfreaks.net/comment/2421756#comment-2421756

Bunch of old projects with AVR's: http://www.hoevendesign.com

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