## 40V High Side Switch?

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I was thinking of using a PFET as a high side switch with an NFET to drive the gate of the PFET. I'm trying to drive 40V to a load but had a question.

If the PFET is rated for a maximum of Vgs = +-20V and Vds = -40V, how do I drive the PFET gate without violating the max Vgs = +-20V? When driving the NFET gate high, the gate of the PFET will be 0V and the Vgs of the PFET = -40V. Is the Vgs spec the limiting and deciding factor for my PFET or is it the Vds spec?

Thanks.

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The schematic you included almost shows what you want to do. Get rid of the capacitors and load, of course. Leaving you with just Q1, Q2, R1, and R2. R2 should be in series with the gate of Q2 and the drain of Q1. The source of Q1 should be grounded. R1 should remain between the source and gate of Q2. R1 and R2 will be forming a voltage divider, protecting Q2's gate from overvoltage.

You have to balance the sizing of R1 + R2 - the smaller they are the higher the power dissipation, but the faster the switching time. +-20V is very standard for power MOSFET gates. I've seen +-30V, and some others are rated for even lower voltages. But +-20V is quite common.

Thanks for the response, it took me a second to realize R1 and R2 were to protect the gate of Q2. Thanks!

Whoa - Not so fast.

What was suggested works for small voltage drops across R2. But ONLY small voltage drops. In this case, small is small with respect to the logic high level of the input signal "ON/OFF". If the input signal is 0-5v, you MIGHT be able to work with 1V drop across R2 (depending on the gate threshold of Q1).

What really works is a resistor between the gate of Q2 and the drain of Q1. But, you have chosen a device that does not give you access to those nodes. For THIS device, you are really limited to Vin = 20V, max. Increasing R2 will NOT help you unless you have at least a 20V ON/OFF input.

The only way that your circuit will "work" is to run Q1 unsaturated. Use it as a current source and choose R1 so that R1*Iq1 < 20V. There is, however, a really big problem with this: The voltage drop across R2 depends on the gate threshold, and it is quite variable (both device-device and over temperature).

So, for this device, you are out of luck. Bad choice. Choose another!

Jim

Until Black Lives Matter, we do not have "All Lives Matter"!

Thanks for the response Jim. I am actually using a discrete NFET and PFET, I just used that device as a schematic to show what I was trying to do.

So you suggest placing R1 between the gate of Q2 and drain of Q1, but doesn't R1 need to be between the source of Q2 and gate to ensure that the device turns off?

No...

R1 as in the schematic. R2 between Q2 gate and Q1 drain.

The worst case gate voltage condition is with Q1 on, so consider the bottom end of R2 grounded (for analysis). If R1=R2, then the forward gate voltage on Q2 is Vin/2. That would be barely safe. I would make R2 about 2X R1. That would make the max forward gate voltage on Q1 to be Vin/3. That should be OK.

You can make R1 and R2 almost any large value you like IF switching speed is not a big issue. But, if you use it for PWM, then you need to be careful.

Jim

Until Black Lives Matter, we do not have "All Lives Matter"!

Thanks for clearing that up, I'll put R2 between the gate of Q2 and drain of Q1.

ka7ehk wrote:
No...

R1 as in the schematic. R2 between Q2 gate and Q1 drain.

The worst case gate voltage condition is with Q1 on, so consider the bottom end of R2 grounded (for analysis). If R1=R2, then the forward gate voltage on Q2 is Vin/2. That would be barely safe. I would make R2 about 2X R1. That would make the max forward gate voltage on Q1 to be Vin/3. That should be OK.

You can make R1 and R2 almost any large value you like IF switching speed is not a big issue. But, if you use it for PWM, then you need to be careful.

Jim

Isn't this exactly what I suggested?

Now that I reread it, yes, I missed your move of R2 - thought you had it in the same place as originally drawn. Sorry!

Jim

Until Black Lives Matter, we do not have "All Lives Matter"!

The original schematic is just fine. This is the standard design of a load switch. Select R2 first, around 100ohm to 1Kohm, and R1:R2 need to be in a 1:10 to 1:100 ratio. Q1 being a logic-level N-MOSFET, and C1/R2 providing a slew rate limiter. R1 pulls Q2's gate to the bus voltage, and when Q1 turns on it pulls Q2's gate to ground, turning the switch on. Only Q2's S-D sees any significant load.

Also this isn't intended to be switched from PWM, it's more of a "power-on/power-off" application switch. It will probably be too slow to do any PWM.

But that will not work in a 40V system where Q1 gate breakdown is only 20V (specified in the first post). Even if the N channel FET saturates at some voltage above ground, it will never be higher than input logic high. If you somehow get that to happen with Vin(high)=5V, the gate will still see 35V and smoke will likely happen.

Jim

Until Black Lives Matter, we do not have "All Lives Matter"!

Oh well yes, in that case you should choose appropriately sized Q1. I feel a little slow for not having understood that from the start. The circuit will work fine with parts properly rated.

Correct, but that was not the original request. Perhaps the OP has these 20V devices in stock and does not want to purchase a new component. Or, maybe it was what was in the parts bin. What-ever.

It is important to note that there is ALSO a 40V minimum Vdg or Vds breakdown requirement for the N channel.

Jim

Until Black Lives Matter, we do not have "All Lives Matter"!