16-bit copies and the TEMP registers on AVR 0-series

Go To Last Post
5 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0


Here is what is said in the megaAVR 0-series on 16 bit copies:

 

The wording seems to indicate that if I read the high byte, I get a read from the TEMP register.

But I'm wondering if there is some constraint with respect to this behavior.   If I read the low byte 10,000 cycles ago, does the high byte still come from the TEMP register, or only if the low and high byte reads are performed with no intermediate instructions.   Any ideas?

 

(I searched for TEMP register but the last post was in 2012.)

Last Edited: Sat. Dec 26, 2020 - 01:29 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I THINK that the contents remains unchanged until another operation that involves that TEMP register. Its not clear to me whether there is just one or, say, one for timers and one for ADC. Or, maybe even one per 16-bit timer. Or, even 1 per 16-bit channel (eg, one for capture, one for compare, one for count, etc -- Microchip does seem pretty "free" with the registers).

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0


ka7ehk wrote:

I THINK that the contents remains unchanged until another operation that involves that TEMP register. Its not clear to me whether there is just one or, say, one for timers and one for ADC. Or, maybe even one per 16-bit timer. Or, even 1 per 16-bit channel (eg, one for capture, one for compare, one for count, etc -- Microchip does seem pretty "free" with the registers).

 

Jim

 

For the newer AVR 0-series chips the TEMP registers are accessible in data space.  It seems there is one TEMP register per peripheral.

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

 

Note also, the mentioned ordering is different (or wrong) from earlier AVR's (ex mega328)...I always remembered that reading vs writing required flip-flopped ordering & so easily noticed here, both reading & writing claim to use matching ordering.

 

 

mega88

To do a 16-bit write, the high byte must be written before the low byte.

For a 16-bit read, the low byte must be read before the high byte.

----------------------------------------------------------------------------

I was never certain whether the new AVR datasheets indicated a new arrangement, or was just a copy/paste duplication typo.

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sat. Dec 26, 2020 - 03:38 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

> If I read the low byte 10,000 cycles ago, does the high byte still come from the TEMP register, or only if the low and high byte reads are performed with no intermediate instructions.   Any ideas?

 

When reading the high byte, you are always reading the temp register, and the temp register only gets updated (from the high byte) when reading the low byte (or directly writing to the temp register). Does not matter when that took place. When writing the low byte, you are writing to the temp register only and no transfer takes place to the low register until you write the high register.

 

read L = read L , H->TEMP

read H = read TEMP

write L = write TEMP

write H = write H, TEMP->L

 

Safe way to do things- always use the 16bit name to read/write.

TCB0.CNT++; //16bit read, ++, 16bit write

read L, H->TEMP, read H (TEMP), ++, write L (TEMP), write H, TEMP->L

 

TCB0.CNTL++;

read L, H->TEMP, ++, write L (TEMP), ?? L is unchanged (stuck in TEMP)

TCB0.CNTH++;

read H (TEMP), ++, write H, TEMP->L, ?? read wrong value from for H (got TEMP, not H), and also corrupted L

 

 

If you always do a 16bit read/write, the only problem remaining is if an isr also does any reading/writing that also uses the TEMP register of the peripheral (can be shared among various 16bit registers in peripheral). Probably not a common occurrence, but I would pay attention to the isr code instead of making every 16bit register access atomic. If a 16bit register is accessed in an isr, you can simply back up and restore the TEMP register. Of course, if both isr and non-isr code are writing to the same register (and not simply sharing the TEMP register) then you are in a different ballgame and will have to deal with it in another way (atomic access in main code), but I imagine that would be quite a rare thing to be doing.

 

 

 

 

Last Edited: Sat. Dec 26, 2020 - 10:44 AM