ATMEGA16/32 Timer1 output control issues

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For a project, I am using the m16/32 16 bit timer1. The current code works fine, but I have output control on OC1A and B turned off. I manage the pins manually. I wanted to switch the code to let the AVR manage the pin states, but I got nowhere last night. I'll relate the code:

I set up the timer for free running, non-PWM mode, count to ffff, 8MHz clock/1
I turn on ICR INT
Set OC pins to outputs, and bring high

When ICR fires, I set OC1A and B to be 512 cycles ahead of TCNT1. I also bring outputs low and turn on OC INTs. FInally, I set output control of each pin to be set-on-match

When each OC INT fires, I turn off output-control for that pin.

The idea is to reduce the jitter of the output signal by using the ICP, but reduce it further by letting the hardware bring the lines high when the compare is matched. Right now, with manual code, I have a problem if both channels are at the same value, as I can't be in both ISR routines at the same time, and my ISR routine (2 lines of C code) takes 36 cycles or so, which is too much error for this application.

However, when i run the above code, I see on my scope that the code works fine until the output-control is turned off. FOr some reason, (I've tried both toggle-mode and set-on-match), the pin makes a momemtary dip to ground, then returns to high.

Anyone have experience with turning off output control on timer outputs while the clock is running and having success?

Jim

Jim Brain

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Quote:
the pin makes a momemtary dip to ground, then returns to high

I haven't tried this in particular, but I did recently have a fight with FOC.
When OC is active, the pin is driven off of a separate (1-bit) OC1x
register, not the PORTx register. OC1x isn't even loaded initially from
the PORTx register (as it was on e.g. the 8535), thus the need for the
FOC1x flag(s).

I assume then that, once the OC is turned off, the pin is once again driven
by the PORTx register, which you originally set high. I dunno about the
glitch, but there is a recommendation for startup to set the DDR After the
timer OC mode is set, so I suspect there should be a similar (reverse)
procedure when the OC is turned off.