Faster A/D clock on mega 8 -> higher power

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We all know about the 200kHz issue in AVR. But in the data sheet of the ATmega8 there is a high speed mode:

Page 193:
By default, the successive approximation circuitry requires an input clock frequency
between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10
bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a
higher sample rate. Alternatively, setting the ADHSM bit in SFIOR allows an increased
ADC clock frequency at the expense of higher power consumption.

Page 203:
Bit 4 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. This mode enables higher
conversion rate at the expense of higher power consumption.

Does this actually mean that I can keep the highest resolution if I accept higher power consumtion? And if that is the case, is it true up to any frequency and what is "higher power consumtion"? 10% increase? 100% increase?

In that AVR:s is this high speed ADC implemented?

Maybe someone can give me at least some of the answers.

/Bengt

My favorites:
1. My oscilloscope, Yokogawa DLM2024.
2. My soldering iron, Weller WD2M, WMRP+WMRT.
3. JTAGICE3 debugger.

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The ADHSM bit was removed:

Changes from Rev. 2486J-02/03 to Rev.2486K-08/03

7. Removed ADHSM completely.

Ralph Hilton

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Arg, that really was a hit in the back!

Any idea why it was removed?

I asume that this means that I have to live with the 200 kHz limit as before, right?

Thanks,
Bengt

My favorites:
1. My oscilloscope, Yokogawa DLM2024.
2. My soldering iron, Weller WD2M, WMRP+WMRT.
3. JTAGICE3 debugger.