Arrowheads in block diagrams in specifications

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Hi guys,

I have been trying to understand some block diagrams in ATmega specs. Specifically, I am trying to figure out the meaning of some arrow heads in SPI block diagram of Atmega8. I see three arrows between SPI control and SPI status register (Figure 57. SPI Block Diagram, ATmega8 spec). Two arrows(SPIF and WCOL) are from SPI control to SPI status register, and one arrow(SPI2X) from SPI status register to SPI control. What do such arrows (arrow-heads) indicate in block diagrams? I see that all the three bits in the arrows (SPIF, WCOL and SPI2X) correspond to SPI Status Register "“ SPSR. Please let me know.

Thanks and regards,
Sandeep K Chaudhary,
University of Waterloo, Canada.

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The usual convention is that an arrow point in the direction of information "flow".

That is, if one block (lets say, A) is connected to another, B, with a line and the line has an arrowhead pointing toward B, then that represents an INPUT to B.

In other words, with this example, something in A will have an effect on B, but B cannot do anything back to A (on that signal path).

Arrows tend to denote one-way signal paths though you do see, once in a while, lines with arrowheads at both ends. Guess that means a two-way path.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Thanks a lot for the quick response, again !

So, in the example of SPI control and SPI status register, can I say that it would be some activity related to SPI control register that would be the reason to set SPIF or WCOL bits? I am getting confused because no where in the descriptions of these bits in SPI status register, I can find any causal effect coming from SPI control register. Please let me know.

Thanks and regards,
Sandeep K Chaudhary,
University of Waterloo, Canada.

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I think you need to do some interpretation, here. first the name, WCOL. It is the "write collision" flag bit. Collisions occur when two things try to do something incompatible at the same time. The text then says:

Quote:
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.

I take it to means that if your code writes to the SPDR while a transfer is underway (the collision, because the SPDR should not be written by code during a transfer), then this bit will be set. In this case, I am assuming that the SPI control register controls access to the SPDR. So, maybe WCOL association is a little weak, but they need to put something, somewhere.

Also, I would not take the those charts and diagrams as absolute. Generally, the text is the defining statement, in my experience.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!