AVR ADC analog bandwith?

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Hello,
has anyone tried to measure actual analog bandwidth of AVR ADC? I'm using it for sampling of kind of funky waveform with fundamental frequency ~42kHz so I'm using equivalent time sampling 2.5MSPS, S&H circuit is evidently fast enough for this. This way I get 59 samples per period which seems to be enough for true-rms calculation. Question is what is the limitation? Datasheet of ATmega48 says 38.5kHz. That seems to me a bit pessimistic because I'm getting almost identical waveform as on the ADC input measured by DSO including much higher harmonics.
With known transfer function I can theoretically apply correction in frequency domain (2.5kB of code memory is plenty to implement some FFT/IFFT for the filter).

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Quote:

Datasheet of ATmega48 says 38.5kHz.

You sure? The normal (10bit) limitation is 200kHz for the ADC clock and 13 ADC clock pulses to convert meaning 200kHz/13 = 15.3kHz

You can get a lower number of bits running the clock faster. I think some have reported 8bits at an ADC clock of 1MHz.

For the signal you mention I'd use an external ADC or some CPu with a much faster internal ADC (perhaps an Xmega-U chip?)

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The AVR a/d can aquire samples at about 9600 samples per second. Each sample uses 13 a/d clocks of about 200KHz. This is all spelled out in the datasheet.

Imagecraft compiler user

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I ask for analog bandwidth, not sampling rate. As I mentioned the signal is periodical and actually generated by the MCU itself so it's extremely easy to implement equivalent time sampling so I have no trouble to get equivalent 2.5MHz even with 6kHz real time sampling. Question is what is bandwidth of the analog circuits from ADC0 pin to S&H (including)?

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I must be missing something. If your signal is 42kHz then Nyquist says you need at least 84kHz to sample it. I just don't see how you plan to achieve that with an ADC limited to 15.3kHz sampling. That was the point I was making.

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Not sure why it matters.

The equivalent input series resistance and S&H capacitance is given in some data sheets.

But if you drive it with a low impedance source, (op-amp), then this ought to not be the limiting stage in the input circuit.

One would generally have a low pass filter on the input to purposefully bandlimit the signal to meet Nyquist criteria.

JC

Edit: Cross post with Cliff

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Tahnks for replies but I have strange feeling we don't understand each other. Analog bandwidth of the ADC has nothing to do with its sampling rate. There are plenty of ADCs with sampling rate around 50MHz but analog bandwidth 750+MHz.
Yes, the realtime sampling rate of the AVR ADC is some 15kHz for full resolution but there are simple techniques that allows equivalent time sampling. So I have realtime sampling around 6.009kHz but I've chosen ratio of sampling rate and the measured signal fundamental frequency so I get stable alias of the input signal with 416x time magnification. Only limiting factor now is the analog bandwidth which I don't know because ATMEL obviously never made the measurement - they probably haven't expected someone will use the ADC this way.

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You want to acquiire data very slowly, but at a constant frequency, from a very fast , very periodic signal, and you want the sample and hold time to be tiny w/r the fast signal?

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Exactly. I can use analog RMS detector or fast ADC or different MCU but question is why should I if the AVR has everything that is required? I wanted to keep the circuit as simple as possible so I choosed this solution. It works just fine but I'm trying to improve accuracy or at least calculate measurement uncertainty and for that I need to know the bandwidth.

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Can you generate a sinusoid waveform (with known amplitude and frequency) at the same frequency than (harmonics of) your funky waveform? That would give you some kind of empirical correction... Perhaps a square waveform would be even easier...

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If you use search in the datasheet pdf, you will find the paragraph that says the analog signal chain is optimized for 4.5KHz freq resp. This is from my memory, so dont flame me if it isnt in every single avr datasheet. Try megs32. Thats the one I've read the most.

Imagecraft compiler user

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Quote:
I'm trying to improve accuracy or at least calculate measurement uncertainty and for that I need to know the bandwidth.
I think the maximal frequency of the signal can be derived from the sample-and-hold time.

From datasheet:

Quote:
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion

Suppose the sample time must not be longer than 1/10 of a signal periode.

For Adc clock = 200 kHz one clock is 5 microsec.
Sample time = 7.5 us.
The signal period should be > 75 us.
Maximal signal frequency is then 13.3 kHz.

Or am I wrong?

Edit:
Now I have realised that the sample-time can be much shorter than sample-and-hold. But I could not find more details about it.

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1.5us is a delay, it doesn't say anything about how long is the sampling gate opened. I've tried to decrease ADC clock rate and the waveform has not changed at all so the sample gate is probably opened for much shorter time than one ADC clock. There are clearly components with frequency 500kHz in the sampled signal (same as on DSO).
I'll search through appnotes and if I won't find any relevant informations I'll try to measure it by sampling some known waveform like bandwidth limited square wave or rather noise with defined spectrum.

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This is out of topic, but can your DSO send the values it displays to a PC (then, you may compute RMS, say, "exactly "and see what your avr computes)

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Hello again,
in case someone is interested I finally made the measurement based on square wave spectrum comparison with DSO.
For AVR at 10MHz, ADC clock /64, Vref=1.1V and x1 gain the bandwidth is approximately 650kHz for -3dB. Equivalent sampling frequency was 5MHz, 103 samples per period (to small memory for better resolution). DSO was sampling at 500MHz directly at ADC0 input with compensated 10MOhm probe - this might be dominant source of meas. uncertainty, have to check it.

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The aperture time, which is the time that that S/H switch is closed, in combination with the S/H cap and the ESR of the sample switch set the equivalent bandwidth. In the case of an AVR, I'd almost be willing to bet that the aperture time is no smaller than 1/2 of ADC clock.

I don't remember the relationship, but it has been well defined in the literature.

And, yes, this bandwidth is primarily important for equivalent-time sampling of repetitive signals. This process is challenging to get right as there are some timing "issues" that are not obvious at first look.

Tektronix used this in the sampling plugins for their vacuum tube scopes in the 1960s. The plugins were full of tunnel diodes and transmission lines and did random sampling. Bandwidth, if I recall correctly, was in the 600MHz area for a host scope with a bandwidth of 35MHz to 45MHz.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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ka7ehk wrote:
The aperture time, which is the time that that S/H switch is closed, in combination with the S/H cap and the ESR of the sample switch set the equivalent bandwidth. In the case of an AVR, I'd almost be willing to bet that the aperture time is no smaller than 1/2 of ADC clock.
This has been covered before, although not in the context of bandwidth:Summary from a loosely related post:
joeymorin wrote:
No conclusive evidence, but some speculation that the S/H cap is switched in at the MUX and REFS update point in the timing diagram (t=0), and switched out at the marked "Sample & Hold" point (t=1.5).

Another freak implemented a software test and concluded that the S/H begins at the "marked" point (1.5 cycles?) and lasts for 1 cycle. This result seems reasonable, as it would allow for 10.5 ADC cycles remaining after the S/H phase completes. This should be enough for a 10-bit successive approximation algorithm. The test methodology seems relatively sound, but I have not reproduced the test.

JJ

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Quote:
For AVR at 10MHz, ADC clock /64, Vref=1.1V and x1 gain the bandwidth is approximately 650kHz for -3dB.
Something is not clear to me:

1. The sample capacitor in adc is about 15 pF.
2. Allowed input impedance is max 10 kOhm.
3. RC constant is 10 kOhm * 15 pF = 0.00000015 = 0.15 us.
4. The capacitor needs 0.9 us to reach 0.997 of input voltage (0.6us for 0.981 ).
5. Then the gate is opened more than half of period.

Is a sample well defined this way?
A picture attached

Attachment(s): 

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I hope I am not wrong, but OP seems to use an AVR as a stroboscope, and tries/managed to correct the fact that the sampler is not perfect (low pass) via calculations. He uses a DSO to verify his corrections are realistic?
And the period of the complicated signal he is interested in is 1/42khz, about 24 uS?
Main issue (apart of potential misunderstanding) I see is "what happens if OP changes his AVR" (which is used at non standard sampling speeds)

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Visovan has described it well.

Since the input time constant (switch R and S/H C) is around 0.15us, the capacitor voltage should follow the input signal (with some reduced amplitude and phase lag). The critical event is when the S/H switch opens. The capacitor will be left with the voltage that was present at that event.

So, in the case where the input time constant is short compared to the aperture time, the critical event is when the switch opens. The input time constant will dominate rather than the aperture time. And the bandwidth should be defined by that time constant, (almost) entirely.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Consider reading the next channel every sample. The sample cap has to slew to the new channel voltage in the 1.5 clock time allocated, or it isn't a good 99% sample. Reading one channel is better, because most real signals don't have large discontinuities, In this case, you can run the prescaler at 0x85 or 0x86 instead of 0x87 to get faster clk, faster samples. If you have a function generator that will produce a 0-5V triangle or sawtooth, it seems like you could sample one cycle of that into an array then print it out. Should be able to calc the error because the input signal ampl is known at each sample. The triangle wave spectrum should have 3rd harmonic down by 1/(3*3), 5th harmonic down by 1/(5*5), 7th down by 1/(7*7) etc.

Imagecraft compiler user

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bobgardner:
About the spectrum analysis - I'm using something similar right now except with square wave and DSO as reference. I've tried that at lower freq.:

It's sampled at 1.25MHz, /128 ADC clock, 103 samples. I'll try to make it properly tomorrow with ATmega644 which has much larger SRAM so I'll have better resolution and few periods at once.
At the moment I'm waiting for ATMEL tech support for S&H details but I don't expect any reasonable response according to my previous experiences with them.

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Visovian wrote:
1. The sample capacitor in adc is about 15 pF.
2. Allowed input impedance is max 10 kOhm.
3. RC constant is 10 kOhm * 15 pF = 0.00000015 = 0.15 us.
4. The capacitor needs 0.9 us to reach 0.997 of input voltage (0.6us for 0.981 ).
5. Then the gate is opened more than half of period.
10K isn't quite correct. Looking at the datasheet (for, say, ATmega328P) Csh = 14 pF, and the ADC has a combined input path resistance of between 1K and 100K. Add to that a nominal 10K source impedance and the R in the TC calculation ranges from 11K to 110K:
(11,000 * 0.000000000014) <= TC <= (110,000 * 0.000000000014)
                 0.154 uS <= TC <= 1.54 uS

This ignores the contribution of parasitic capacitance (pin, PCB, etc.).

JJ

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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I once built an RMS meter using an AVR and random
sampling. I checked it with a sine-signal.
It gave quite accurate results up to 100kHz.
At 500kHz the error was 10%, at 1MHz the error was 30%.
If you send me a PM with your e-mail address
I can send you an ELEKTOR article that covers that
topic. By under-sampling it is even possible to
built an SDR receiver with frequency up to 600kHz.

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Except 16MHz divided by 128 is 125KHz, not 1.25MHz. And that is the a/d clock. 125KHz over 13 is 9600 samples per sec just like the datasheet says. This gives about 4KHz freq resp. Good for speech.

Imagecraft compiler user

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bobgardner:
I somehow don't get what are you responding to. Firstly I'm using 10MHz XTAL, secondly 1.25Ms/s is equivalent sampling frequency of the method I used not ADC clock. Actual ADC sampling rate is of course only 10E6/128/13 = 6.0096kHz but that's completely irrelevant because Nyquist theorem is now related to equivalent sampling frequency 1.25MHz. That's the point of the method.

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smaslan wrote:
Hello again,
in case someone is interested I finally made the measurement based on square wave spectrum comparison with DSO.
For AVR at 10MHz, ADC clock /64, Vref=1.1V and x1 gain the bandwidth is approximately 650kHz for -3dB. Equivalent sampling frequency was 5MHz, 103 samples per period (to small memory for better resolution). DSO was sampling at 500MHz directly at ADC0 input with compensated 10MOhm probe - this might be dominant source of meas. uncertainty, have to check it.

Interesting numbers, so this makes your original 2.5Msps about 4x the bandwidth ?
Probably still worthwhile, as it tends to ensure the S&H bandwidth dominates, but FFT is probably not valid to 2.5Msps.

Have you tried this with any other AVR with a better ADC ?

I have been wondering how much a sampling approach would yield, on an ADC with a 2MHz clock.

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smaslan wrote:
Datasheet of ATmega48 says 38.5kHz.
This figure is the maximum Nyquist frequency of the ADC and is a measure of the digital bandwidth, not that of the analog signal path. It is derived from the specified maximum ADC clock of 1 MHz. At 13 ADC cycles for a conversion that's a sample rate of 76.923 kHz, leaving a Nyquist frequency of 38.462 kHz.

For devices with differential channels, the input bandwidth is limited to 4 kHz due to the gain amplifier.

As already discussed the inherent bandwidth of the analog signal path is (likely) primarily a function of the TC of the S/H cap network. As per this online calculator, with a source impedance of 10K, the cut-off frequency (-3dB) is between about 103.347 kHz and 1.033 MHz. With a source impedance approaching zero, the cut-off frequency is between 113.682 kHz and 11.368 MHz.

As for getting a response from Atmel w.r.t. real analog bandwidth, I suspect it has simply never been characterised.

JJ

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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But it can be measured by sampling a known input signal. Agree?

Imagecraft compiler user

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bobgardner wrote:
But it can be measured by sampling a known input signal. Agree?
It can be estimated algorithmically, and you can probably arrive at an accurate limit.

I would propose a different method for measuring the real TC of the S/H network. Fuse a test subject AVR for external clock, and rig another AVR to generate a slowish clock (16 kHz) on one GPIO pin, while polling another GPIO pin as a clock stop signal (pull-up enabled). When the clock stop signal goes low, stop the clock.

On the test subject AVR, write code that sets the ADC prescaler to the maximum of 128. Start a conversion. Count cycles until the S/H gate is open. Configure the GPIO pin connected to the clock generating AVR's "clock stop" pin as an output, driving it low. This stops the clock to the test subject AVR. If correctly timed, the S/H gate will be frozen open. You can then use a DSO and a signal generator to determine the real TC of the S/H network.

Three things:

    1) Although the AVR is fully static, this kind of clock manipulation may have side-effects. 2) As no conclusive literature specifies the moments at which the S/H gate is opened and closed, this will have to be arrived at by experimental trial and error.
    3) The expected TC is low enough that the effects of the DSO probe and signal generator will need to be factored in. A control consisting of just the signal generator and DSO can characterise those effects.
JJ

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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So I did the measurement on ATmega644. Conditions:
XTAL: 20MHz
ADC clock: /128 = 156.25kHz
ADC real time sampling rate: 12.01923kHz (free run)
ADC ref: 1.1V
ADC gain: x1
Referece signal: square 24.06739kHz
Input Z: ~150 Ohm
Samples count: 831 per ref. signal period, 16 periods
Equivalent sampling rate: 20Ms/s

Looks similar to ATmega48. But I've noticed one thing - there are visible spikes in signal measured by the DSO. It is clearly caused by sampling current into internal capacity. I'll try to figure out how to use this to measure internal Z since it's undefined (1 to 100k?).

Edit: Corrected decimal point.

Last Edited: Fri. Jul 5, 2013 - 05:20 PM
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joeymorin: That's hardcore method. :D But yes, it does sense but I think I'll try to use the spikes produced by the S&H.

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Quote:

It is clearly caused by sampling current into internal capacity.

"Clearly"?

"Clearly, I have two guesses:
1) The signal is actually overshooting, with transmission line effects and all that, and the DSO is doing an accurate job of showing what is really there; or
2) If you tweak the adjustment screw on your 'scope probe the artifact will go away.

I'll bet you a session of imbibing virtual cold ones that an AVR channel directly connected to a high-drive signal that you described is going to affect the signal in any way, during S/H or otherwise. The input impedance is just too high.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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smaslan wrote:
ADC real time sampling rate: 12019.23kHz (free run)
I think you mean Hz. And it's wrong anyway. Free-run on the'48 is 13.5 ADC cycles between samples. Real sample rate: 11.5740 kHz.

JJ

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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joeymorin wrote:
smaslan wrote:
ADC real time sampling rate: 12019.23kHz (free run)
I think you mean Hz. And it's wrong anyway. Free-run on the'48 is 13.5 ADC cycles between samples. Real sample rate: 11.5740 kHz.
JJ

My mistake, it's of course in Hz but it's not 13.5 cycles! I was confused few days ago when I was reading the datasheet and I thought it's 13.5 also but then I looked at Fig. 24-7 which shows it's 13 cycles and it actually is according to ADC ISR period measurement.

And about those spikes in a signal: I'm pretty sure about this. I tried to generate pulse on GPIO with the ADC trigger, I synced the DSO to that and the spike was alway in same position and always had correct polarity according to last sampled voltage. It's getting bigger with the input impedance of course. The amplitude is not big, ~50mV. The input Z is of course just a guess, I don't have any way to measure it. 150Ohm resistor doesn't mean Z=150Ohm - there is for sure series inductance and the capacitor I'm using for AC coupling is also not perfect.

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smaslan wrote:
... but it's not 13.5 cycles! I was confused few days ago when I was reading the datasheet and I thought it's 13.5 also but then I looked at Fig. 24-7 which shows it's 13 cycles and it actually is according to ADC ISR period measurement.
So it is, I stand corrected. I'd assumed that, since free-running is an auto-triggered mode, it followed the specs in table 24-1. I'd missed figure 24-7 above the table. A short test program confirms it.

JJ

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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smaslan wrote:

And about those spikes in a signal: I'm pretty sure about this. I tried to generate pulse on GPIO with the ADC trigger, I synced the DSO to that and the spike was alway in same position and always had correct polarity according to last sampled voltage. It's getting bigger with the input impedance of course. The amplitude is not big, ~50mV.

Z would be hard to measure/derive by spike.
One estimate could be to add series R until the -3dB point halves, but the Pin C effect will distort this a little.

In such an app, you usually drive ADC pins with the lowest impedance anyway, so if the S+H R is 5k or 10k does not matter too much - you cannot do anything about it.

Measuring the over-sampling bandwidth is a more practical number, or you could also check Rise time.

( the curve above suggests ~680ns rise time, what would be interesting is if the ~13.6 indicated samples in that time, seem to interpolate as expected ? )

If you feed the DSO from a separate buffered signal + low pass filter of the same roll off, you should see similar Rise times.

I did find
AVR1300: Using the Atmel AVR XMEGA ADC
This has a discussion of ADC clocks, and ADC (over)sampling, and for the XMega that is ~ 2Msps, and a 2MHz ADC clock. and there is a plot of (over) sampling BW vs added Series resistance.
A Drive impedance of under 500 ohms is needed to avoid extra roll-off effects.

They mention example values of 4.5k and 5pF

Looks like a rough benchmark is over-sampling limit is about the same as the ADC clock limit ?

Last Edited: Sat. Jul 6, 2013 - 01:24 AM
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Quote:

And about those spikes in a signal: I'm pretty sure about this.

So, you are putting a "hard" signal, with good drive, into a high-impedance input pin on the AVR.

Now, I'm just an old bit-pusher. So I make the analogy that if you throw the ball hard into a wall without much give, isn't it going to bounce back?

Tell you what--put your signal into the pin and watch it on the 'scope. Repeat your test and verify these spikes. Then, keep watching and hold your AVR in reset. They most be gone, now, 'cause the S/H ain't doing anything.

And/or, if you care to, keep watching your 'scope while you roate between ADC channels every second or so. During the "off" seconds, the S/H wont ever be looking at that channel.

Now, as the S/H is only for a small time each ADC conversion, how is it that it seems to be causing these spikes EVERY TRANSITION of your input signal which is not synchonized to the ADC conversions?

And the last magic trick is to turn off the ADC (and maybe the digital input buffers) while observing your symptoms. Do they remain?

What about when there is no connection to the AVR--just a short wire, simulating the signal generator, the 'scope connection, and the AVR pin?

What results do you get when connecting to a non-ADC pin?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:
Quote:

And about those spikes in a signal: I'm pretty sure about this.

So, you are putting a "hard" signal, with good drive, into a high-impedance input pin on the AVR.

Now, I'm just an old bit-pusher. So I make the analogy that if you throw the ball hard into a wall without much give, isn't it going to bounce back?

The impedance was actually higher than 150Ohm - I had passive drive circuit with osme divider and lousy cap. Now I have fast OPAMP there and 50Ohm non-inductive series resistor (without it my AD8041 oscillates). For this setup the spikes are gone and the bandwidth increased to some 550kHz for -3dB (this might be also used for Z estimation).

Quote:

Tell you what--put your signal into the pin and watch it on the 'scope. Repeat your test and verify these spikes. Then, keep watching and hold your AVR in reset. They most be gone, now, 'cause the S/H ain't doing anything.

And/or, if you care to, keep watching your 'scope while you roate between ADC channels every second or so. During the "off" seconds, the S/H wont ever be looking at that channel.

Now, as the S/H is only for a small time each ADC conversion, how is it that it seems to be causing these spikes EVERY TRANSITION of your input signal which is not synchonized to the ADC conversions?

And the last magic trick is to turn off the ADC (and maybe the digital input buffers) while observing your symptoms. Do they remain?

What about when there is no connection to the AVR--just a short wire, simulating the signal generator, the 'scope connection, and the AVR pin?

What results do you get when connecting to a non-ADC pin?

At first I also thought it's some kind of interference so of course I tried all you've just described and the spikes are present only at active ADC input only while sampling and only if last sample had different level than the new one.
Btw with 22k input resistor the length of the spike is some 5us so the dominant bw. limiting factor is probably input Z and Ch cap, not sampling time.