Our app runs on an xmega256a3. We run our watchdog timer at the 8 second configuration. We sleep the processor for extended periods. But we leave the WDT enabled during sleep. So if our sleep goes longer than 7.5 seconds, we wake up briefly every 7.5 seconds to reset the watchdog.
Now I've stumbled on this bit of info from an AVR application note (AVR1310, doc8034.pdf):
The typical accuracy of the clock for the WDT is +/-30% (please refer to datasheet for exact information on accuracy of the clock).
When we refer to the xmega256a3 data sheet though, we find scant little on the ULP Oscillator:
Output frequency 32 kHz ULP OSC
T = 85°C, VCC = 3.0V
26 kHz
Part of me thinks we should just go with the 30% and go adjust our minimal watchdog reset time to 5.5 seconds (70% of 8 seconds). But what's odd, is that we have around 500 of these devices running, and I don't think any of them have displayed a tendency to reset on long sleeps when the ought not. So it almost seems as if 7.5 seconds (roughly 93% of 8s) is good enough. And the specific datasheet doesn't seem to give a specific range.
