AVR Freaks

Atmega48A/88A/168A/328A+PA datasheet
doc: 8271G-AVR-02/2013

In section 20.7 there is a bug in the example

The assembly example is:

Here the USART Data register Empty flag is checked instead of the USART Receive Complete flag.
The fun part is that the C code example below that does have the correct code:

The low power oscillator itself is a bug imho.  I have seen it cause all manner of glitchy, impossible to debug problems, which are magically cured by going back to the full swing oscillator.

Device: ATmega328PB Xplained Mini User Guide 42469B, updated 2015-08

Summary: PD1 and PD0 ATmega328PB pins incorrectly swapped in "Table 2-10 J104 USART Header" on p.17. (ATmega328PB Xplained Mini schematic A09-2523 Rev. 4, 04.01.2017, is correct.)

AVR910: In-System Programming APPLICATION NOTE

The document states that Programming Enable command ($AC 53 xx yy) gets reply ($zz AC 53 xx).

That is not correct. It does not echo AC in the second byte of the reply.

I believe there an error in the ATmega48A.../328/P datasheet, dated 2018, DS40002061A.

On page 131, Section 16.9.1, the second paragraph starting "The Input Capture ..." states the need to deal with "resolution of the counter", but I think they mean "range of the counter".

Edit: Or am I missing something with respect to the term "resolution"?

Device: ATtiny212/ATtiny412

Summary: Wrong mux table in the datasheet

Datasheet: Rev. A - 01/2017 

Here is the right mux table:

ATTINY1614

Datasheet says on pg337; "When the USART is set in one-wire mode, the transmitter and the receiver share the same RxD I/O pin."; (that is wrong)

One-Wire pin is the TXD pin, NOT THE RXD PIN

Microchip has confirmed that TXD is the correct pin for One-Wire. I'm in the process of trying to get Microchip to update the datasheet.

Also not specified in the datasheet for One-Wire mode...

If TX pin is set as output, ODME "Open Drain Mode Enable" does not work.
so TX port must NOT be set as output when using ODME "Open Drain Mode Enable".
This is Not specified in the datasheet.

The following statement from pg340 about one wire setup is vague.
For setting the USART in One-Wire mode, the following initialization sequence is recommended:
1) Set the TxD/RxD pin value high, and optionally set the XCK pin low.
*Needs clarification, what does "Set the TxD pin value high" mean, pullup resistors? or set as output?
*testing shows that in open drain mode, pin should NOT be set as output
2) Optionally, write the ODME bit in the USARTn.CTRLB register to '1' for Wired-AND functionality.
3) Set the TxD/RxD and optionally the XCK pin as an output.
4) Select the baud rate and frame format.
5) Select the mode of operation (enables XCK pin output in Synchronous mode).
6) Enable the transmitter or the receiver, depending on the usage

Tested and working method for 1 wire.
1) Do NOT set TxD pin as output
2) Enable Pullup Resistor on TxD pin if NOT using external pullup.
3) set bit LBME "Loop-back Mode Enable"
4) set bit ODME "Open Drain Mode Enable"
5) Use TxD pin for Transmit and Receive operations.
6) Enable the transmitter or the receiver, depending on the usage

got it done, https://www.avrfreaks.net/forum/attiny1614-one-wire-errata-datasheet-errors

--- USI SPI Compliance ---

The AVR Universal Serial Interface (USI) Three-wire external clock modes are compliant with SPI modes 1 and 3. The datasheet (e.g., ATtiny84A) partially correctly states that the "USI clock modes correspond to SPI data modes 0 and 1". However, the datasheet USI Three-wire Mode Timing Diagram figure and supporting text are ambiguous and/or fundamentally incorrect with regards to how the USI actually functions; most importantly, the described clock edge phase association with DI-sample/DO-change events are either inconsistent or wrong.

I have notified Microchip, who said they are looking into it.

The following figure summarizes the USI external clock modes functionality:

The following ATtiny84A program characterizes the USI DI-sample/DO-change timing on a standalone chip without need for an oscilloscope to observe results (although a scope is very useful):

#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/cpufunc.h>
#include <util/delay.h>
#include <stdint.h>
#include <stdbool.h>

// Purpose:
// Discover USI Three-wire external clock mode DI and DO timing wrt USCK
// without external connections to device pins (self-acquisition).

// Results summary (USICS1 = 1):
//  USICS0 = 0 with normally high USCK: This USI usage mode looks the same as SPI mode 3 (CPOL=1, CPHA=1)
//  USICS0 = 1 with normally low USCK:  This USI usage mode looks the same as SPI mode 1 (CPOL=0, CPHA=1)
//  USICS0 = 0 with normally low USCK:  This USI usage mode does not look any SPI mode
//  USICS0 = 1 with normally high USCK: This USI usage mode does not look any SPI mode

// Method:
//  1. Manually generate 16 USCK edges for each simulated transfer.
//  2. Use Pin Change interrupts for DO and USCK to capture time, pin state, and USICNT for each pin state change.
//  3. Apply simulated DI pin input, then capture the time when it is sampled by the USI for each Data register bit.

// Detailed observations for all combinations of USICS0 and normal USCK clock states:
#define USICS0_VALUE        0   // USI clock source edge select (0 or 1): 0=="positive edge", 1=="negative edge"
#define NORMAL_USCK_STATE   1   // USI USCK normal (before and after transfer) state (0 or 1): 0==low, 1==high
//  USICS0 = 0 with normally high USCK (This USI usage mode looks the same as SPI mode 3 (CPOL=1, CPHA=1)):
//  DO is changed on leading  (falling) USCK edges 1(MSB),3(b6),5(b5),7(b4),9(b3),11(b2),13(b1),15(LSB); (not changed at write to USIDR)
//  DI is sampled on trailing (rising)  USCK edges 2(MSB),4(b6),6(b5),8(b4),10(b3),12(b2),14(b1),16(LSB)

//#define USICS0_VALUE      1   // USI clock source edge select (0 or 1): 0=="positive edge", 1=="negative edge"
//#define NORMAL_USCK_STATE 0   // USI USCK normal (before and after transfer) state (0 or 1): 0==low, 1==high
//  USICS0 = 1 with normally low USCK (This USI usage mode looks the same as SPI mode 1 (CPOL=0, CPHA=1)):
//  DO is changed on leading  (rising)  USCK edges 1(MSB),3(b6),5(b5),7(b4),9(b3),11(b2),13(b1),15(LSB); (not changed at write to USIDR)
//  DI is sampled on trailing (falling) USCK edges 2(MSB),4(b6),6(b5),8(b4),10(b3),12(b2),14(b1),16(LSB)
//  MSB is sampled (DI) on 2nd USCK edge (USICNT=1 to 2); LSB is sampled (DI) on 16th USCK edge (USICNT=15 to 0)

//#define USICS0_VALUE      0   // USI clock source edge select (0 or 1): 0=="positive edge", 1=="negative edge"
//#define NORMAL_USCK_STATE 0   // USI USCK normal (before and after transfer) state (0 or 1): 0==low, 1==high
//  USICS0 = 0 with normally low USCK (This USI usage mode does not look any SPI mode):
//  DO is changed to MSB at write to USIDR,
//  then on trailing (falling) USCK edges 2(b6),4(b5),6(b4),8(b3),10(b2),12(b1),14(LSB),16(next MSB)
//  DI is sampled on mixed USCK edges; rising 3(MSB),5(b6),7(b5),9(b4),11(b3),13(b2),15(b1), and falling 16(LSB)

//#define USICS0_VALUE      1   // USI clock source edge select (0 or 1): 0=="positive edge", 1=="negative edge"
//#define NORMAL_USCK_STATE 1   // USI USCK normal (before and after transfer) state (0 or 1): 0==low, 1==high
//  USICS0 = 1 with normally high USCK (This USI usage mode does not look any SPI mode):
//  DO is changed to MSB at write to USIDR,
//  then on trailing (rising) USCK edges 2(b6),4(b5),6(b4),8(b3),10(b2),12(b1),14(LSB),16(next MSB)
//  DI is sampled on mixed USCK edges; falling 3(MSB),5(b6),7(b5),9(b4),11(b3),13(b2),15(b1), and rising 16(LSB)

// Hardware abstraction for bit access:
struct bits
{
  uint8_t b0:1;
  uint8_t b1:1;
  uint8_t b2:1;
  uint8_t b3:1;
  uint8_t b4:1;
  uint8_t b5:1;
  uint8_t b6:1;
  uint8_t b7:1;
} __attribute__((__packed__));
#define BIT(portLetter, bitNumber, registerName) ((*(volatile struct bits*)&registerName##portLetter).b##bitNumber)
// portLetter = A-D, bitNumber = 0-7, registerName = "PORT", "PIN", or "DDR"
#define INPUT   0   // DDR bit = input
#define OUTPUT  1   // DDR bit = output

//  Pin usage map:
//  ATtiny84A Port Functions
//  Name    Num FuncA   FuncB   FuncC   FuncD   FuncE   FuncF       Usage
//  ----    --- -----   -----   -----   -----   -----   -----       -----
//  PA7     6   ADC7    OC0B    ICP1    -       -       PCINT7  ==
//  PA6     7   ADC6    DI      SDA     MOSI    OC1A    PCINT6  ==  USI DI
//  PA5     8   ADC5    DO      MISO    OC1B    -       PCINT5  ==  USI DO, PCINT5
//  PA4     9   ADC4    USCK    SCL     T1      -       PCINT4  ==  USI USCK, PCINT4
//  PA3     10  ADC3    T0      -       -       -       PCINT3  ==
//  PA2     11  ADC2    AIN1    -       -       -       PCINT2  ==
//  PA1     12  ADC1    AIN0    -       -       -       PCINT1  ==
//  PA0     13  ADC0    AREF    -       -       -       PCINT0  ==  scope trigger
//
//  PB3     4   RESET   dW      -       -       -       PCINT11 ==  dW
//  PB2     5   INT0    OC0A    CKOUT   -       -       PCINT10 ==
//  PB1     3   XTAL2   -       -       -       -       PCINT9  ==  resonator
//  PB0     2   XTAL1   CLKI    -       -       -       PCINT8  ==  resonator
//
//  Vcc     1
//  GND     14

// Pin assignments
#define USI_DI(r)           BIT(A, 6, r)    // USI 3-wire mode DI
#define USI_DO(r)           BIT(A, 5, r)    // USI 3-wire mode DO
#define USI_USCK(r)         BIT(A, 4, r)    // USI 3-wire mode USCK
#define SCOPE_TRIG(r)       BIT(A, 0, r)    // scope trigger

#define PCINT_DO    PCINT5                  // DO pin change interrupt mask bit
#define PCINT_USCK  PCINT4                  // USCK pin change interrupt mask bit

// Constants
const double        timeTick    = 40e-6;    // time clock tick length (sec)
#define nEdges      16                      // USCK edges per transfer
#define nBits       8                       // data bits per transfer
const uint8_t       endOfTime   = 255;      // time stops here
const uint8_t       delayUsck   = 10;       // delay before first USCK edge (use 10 to "tag" 1st edge for capture readability)
const uint8_t       usckWidth   = 10;       // half of USCK period (use 10 to "tag" edges in multiples of 10 for capture readability)
const uint8_t       txData      = 0xaa;     // DO transmit data--need alternating bit values to force DO change at each update
const double        delayTransfer = 2 * usckWidth * timeTick;   // delay between transfers (sec)

// RAM variables
volatile uint8_t    time;                       // runs from 0 to 255 * timeTick seconds
volatile uint8_t    tNextEdge;                  // scheduled time for USCK edge output change
volatile uint8_t    pinChangeCount;             // DO/USCK pin change counter (pin change capture buffer index)
volatile uint8_t    captureTimeUsck[nEdges];    // capture buffer for time of USCK pin change
volatile uint8_t    captureStateUsck[nEdges];   // capture buffer for USCK pin state at pin change
volatile uint8_t    captureUsicntUsck[nEdges];  // capture buffer for USICNT at USCK pin change
volatile uint8_t    captureTimeDo[nEdges];      // capture buffer for time of DO pin change
volatile uint8_t    captureStateDo[nEdges];     // capture buffer for DO pin state at pin change
volatile uint8_t    captureUsicntDo[nEdges];    // capture buffer for USICNT at DO pin change
volatile uint8_t    captureTimeDi[nBits];       // capture buffer for time of DI pin sample==1 for each USI Data Register Rx bit
volatile uint8_t    delayDi;                    // DI pin stimulus (pin state set to 1) delay
volatile uint8_t    bitDi;                      // DI capture bit number (DI capture buffer index)

static inline void Break(void)
{
    asm volatile("break\n\t"::);    // breakpoint instruction
}

ISR(PCINT0_vect)
{
    // USI DO and USCK pin change interrupt (handle only one at a time)
    if ( PCMSK0 & (1<<PCINT_DO) )
    {
        captureStateDo[pinChangeCount]  = USI_DO(PIN);          // capture DO pin state
        captureTimeDo[pinChangeCount]   = time;                 // absolute timestamp (includes delayUsck)
        captureUsicntDo[pinChangeCount] = USISR & ((1<<USICNT3) | (1<<USICNT2) | (1<<USICNT1) | (1<<USICNT0) ); // capture USI USCK edge counter
    }
    else if ( PCMSK0 & (1<<PCINT_USCK) )
    {
        captureStateUsck[pinChangeCount]    = USI_USCK(PIN);        // capture USCK pin state
        captureTimeUsck[pinChangeCount]     = time;                 // absolute timestamp (includes delayUsck)
        captureUsicntUsck[pinChangeCount]   = USISR & ((1<<USICNT3) | (1<<USICNT2) | (1<<USICNT1) | (1<<USICNT0) ); // capture USI USCK edge counter
    }

    if ( pinChangeCount < nEdges )
    {
        pinChangeCount++;
    }
}

ISR(TIM0_COMPA_vect, ISR_NOBLOCK)   // non-blocking to allow USI DO pin change ISR
{
    // Time clock tick service

    // DI stimulus
    if ( time == delayDi )
    {
        USI_DI(PORT) = 1;       // set USI DI pin
        _NOP(); _NOP();         // ensure sample setup time (input synchronizer delay) is met in case USCK edge is scheduled for same time
    }

    // USCK generator
    if ( (USISR & (1<<USIOIF)) == 0 )
    {
        if ( time == tNextEdge )            // time for next edge?
        {
            USI_USCK(PIN) = 1;              // toggle USCK pin
            tNextEdge = time + usckWidth;   // schedule next edge
        }
    }

    // If no more time, then stop time clock
    if ( time == endOfTime )
    {
        TIMSK0 = 0;
    }

    time++;
}

void RunTransferClockAndDiStim( void )
{
    USI_DI(PORT)    = 1;            // scope trigger
    USI_DI(PORT)    = 0;            // clear USI DI pin
    USIDR           = txData;       // at USIDR write: if USCK(pin) == USICS0_VALUE, then DO is changed to MSB, else DO unchanged

    _delay_us( delayTransfer * 1e6 );

    cli();

    time            = 0;            // reset time
    tNextEdge       = delayUsck;    // schedule first USCK edge
    USISR           = 1<<USIOIF;    // clear USI USCK edge counter overflow flag, and reset count
    TIMSK0          = 1<<OCIE0A;    // enable time interrupt; start transfer

    sei();

    while ( (TIMSK0 & (1<<OCIE0A)) != 0 );      // wait until ISR stops time clock
}

int main(void)
{
    uint8_t i;

    USI_DI(DDR)         = OUTPUT;
    USI_DO(DDR)         = OUTPUT;
    USI_USCK(DDR)       = OUTPUT;
    SCOPE_TRIG(DDR)     = OUTPUT;

    USI_USCK(PORT)      = NORMAL_USCK_STATE;    // when does this need to occur wrt USISR, USICR?
    SCOPE_TRIG(PORT)    = 0;

    _delay_us( 10 * delayTransfer * 1e6 );

    // Configure Timer/Counter 0 (8-bit) for use as time clock
    // Mode 2, Clear Timer on Capture (CTC), TOP = OCR0A
    TCCR0A = 2<<WGM00 | 0<<COM0A0;  // non-PWM, OC0A/OC0B disconnected
    //TCCR0B = 1<<CS00;             // 1x prescale
    //TCCR0B = 2<<CS00;             // 8x prescale
    TCCR0B = 3<<CS00;               // 64x prescale
    //TCCR0B = 4<<CS00;             // 256x prescale
    //TCCR0B = 5<<CS00;             // 1024x prescale
    OCR0A = ((timeTick)*F_CPU)/64 - 1;
    //TIMSK0 = 1<<OCIE0A;           // enable time interrupt

    USICR   = (1<<USIWM0) | (1<<USICS1) | (USICS0_VALUE<<USICS0);   // USI mode = 3-wire; clock source = external

    // Pre-fill capture buffers with invalid data that indicates non-capture
    for ( i = 0; i < nEdges; i++ )
    {
        captureTimeUsck[i]      = 0;
        captureStateUsck[i]     = 255;
        captureUsicntUsck[i]    = 255;
        captureTimeDo[i]        = 0;
        captureStateDo[i]       = 255;
        captureUsicntDo[i]      = 255;
    }

    sei();

    GIMSK   = 1<<PCIE0;
    // Discover USCK change timing/selftest (only need single transfer)
    pinChangeCount = 0;
    PCMSK0  = 1<<PCINT_USCK;        // enable only USI USCK pin change interrupt
    RunTransferClockAndDiStim();    // let pin change ISR capture USCK change timing

    // Discover DO update (USI Data Register shifted out) timing (only need single transfer)
    pinChangeCount = 0;
    PCMSK0  = 1<<PCINT_DO;          // enable only USI DO pin change interrupt
    RunTransferClockAndDiStim();    // let pin change ISR capture DO update timing
    GIMSK   = 0;                    // disable external interrupts

    // Discover DI sample timing for each USI Data Register bit shifted in
    delayDi = endOfTime;        // set DI delay sweep to initial value (sweep from after last (LSB) down to first (MSB) bit)
    for ( bitDi = 0; bitDi < nBits; bitDi++ )   // watch for last bit shifted in (LSB) first
    {
        do
        {
            RunTransferClockAndDiStim();    // let time clock ISR stimulate DI at time==delayDi
            if ( USIBR & (1<<bitDi) )       // did this bit detect DI stimulus in this transfer?
            {
                captureTimeDi[bitDi] = delayDi; // yes, capture DI delay timestamp (absolute, includes delayUsck)
                SCOPE_TRIG(PORT) = 1;
                SCOPE_TRIG(PORT) = 0;
                break;                      // skip to next bit, starting with capture delay of this bit
            }
            else
            {
                delayDi--;                  // no, try next DI stimulus delay for this bit
            }
        }
        while ( delayDi >= 0 );             // should never get to delayDi==0 (should detect MSB before)
    }

    Break();
}

The following ATmega328P SPI master and ATtiny84A USI Three-wire mode slave programs demonstrate which USI external clock modes are compliant with SPI modes, and which are not:

ATmega328P SPI master code:

#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <stdint.h>

// Test data transfer exerciser using SPI in Master mode
#define SPI_MODE_CPOL_CPHA  0       // clock polarity and phase, [CPOL:CPHA] = 0, 1, 2, or 3
// SPI mode 0 (CPOL=0, CPHA=0): SCK idle  low; read MISO on SCK lead  (rise); write MOSI on SCK trail (fall) or half SCK cycle before 1st lead (rise); MOSI normally high (regardless of last bit)
// SPI mode 2 (CPOL=1, CPHA=0): SCK idle high; read MISO on SCK lead  (fall); write MOSI on SCK trail (rise) or half SCK cycle before 1st lead (rise); MOSI normally high (regardless of last bit)
// SPI mode 1 (CPOL=0, CPHA=1): SCK idle  low; read MISO on SCK trail (fall); write MOSI on SCK lead  (rise); MOSI normally same as last bit
// SPI mode 3 (CPOL=1, CPHA=1): SCK idle high; read MISO on SCK trail (rise); write MOSI on SCK lead  (fall); MOSI normally same as last bit

// Hardware abstraction for bit access:
struct bits
{
  uint8_t b0:1;
  uint8_t b1:1;
  uint8_t b2:1;
  uint8_t b3:1;
  uint8_t b4:1;
  uint8_t b5:1;
  uint8_t b6:1;
  uint8_t b7:1;
} __attribute__((__packed__));
#define BIT(portLetter, bitNumber, registerName) ((*(volatile struct bits*)&registerName##portLetter).b##bitNumber)
// portLetter = A-D, bitNumber = 0-7, registerName = "PORT", "PIN", or "DDR"
#define INPUT   0   // DDR bit = input
#define OUTPUT  1   // DDR bit = output

// ATmega328P pin assignments
#define SPI_SS_(r)      BIT(B, 2, r)    // SPI slave select -- output to slave
#define SPI_MOSI(r)     BIT(B, 3, r)    // SPI MOSI -- output to slave
#define SPI_MISO(r)     BIT(B, 4, r)    // SPI MISO -- input from slave
#define SPI_SCK(r)      BIT(B, 5, r)    // SPI SCK -- output to slave
#define ERROR_LED_(r)   BIT(D, 1, r)    // transfer integrity error indicator (note: active-low)

const double    WAIT_SLAVE_SELECT   = 2.0e-6;   // wait time (seconds) for slave to prepare for transfer after select
const double    WAIT_SLAVE_DESELECT = 1.0e-6;   // wait time (seconds) for slave to process Tx data after deselect
const uint8_t   TX_ONLY_MSB_AND_LSB = 0x81;     // Tx only MSB and LSB to highlight failure mode and for better trace readability

static uint8_t  txData;
static uint8_t  rxData;

int main(void)
{
    cli();

    SPI_MISO(DDR)   = INPUT;
    SPI_SS_(DDR)    = OUTPUT;
    SPI_MOSI(DDR)   = OUTPUT;
    SPI_SCK(DDR)    = OUTPUT;
    ERROR_LED_(DDR) = OUTPUT;

    SPCR    = (0<<SPIE) | (1<<SPE) | (0<<DORD) | (1<<MSTR) | ((SPI_MODE_CPOL_CPHA) << CPHA);        // master, MSB-first

    //SPCR  |= 0<<SPR0; SPSR = 1<<SPI2X;    // Fsck = Fclk/2
    //SPCR  |= 0<<SPR0;                     // Fsck = Fclk/4
    //SPCR  |= 1<<SPR0; SPSR = 1<<SPI2X;    // Fsck = Fclk/8
    SPCR    |= 1<<SPR0;                     // Fsck = Fclk/16
    //SPCR  |= 2<<SPR0; SPSR = 1<<SPI2X;    // Fsck = Fclk/32
    //SPCR  |= 2<<SPR0;                     // Fsck = Fclk/64
    //SPCR  |= 3<<SPR0; SPSR = 1<<SPI2X;    // Fsck = Fclk/64
    //SPCR  |= 3<<SPR0;                     // Fsck = Fclk/128

    ERROR_LED_(PORT) = 1;                   // (note: active-low error indicator)
    SPI_SS_(PORT) = 1;                      // deselect slave

    // To see failure on scope, trigger on ERROR_LED_ or SPI_SS_ positive-pulse-width-greater-than non-error condition width
    // To see success on scope, trigger on SPI_SS_ positive-pulse-width-less-than error condition width

    // Repeatedly transmit same (fixed) data; expect exact data (echo) received from slave
    // after data pipeline fills/flushes on first transfer.
    txData = TX_ONLY_MSB_AND_LSB;

    while ( 1 )
    {
        SPI_SS_(PORT) = 0;                          // select slave
        _delay_us( WAIT_SLAVE_SELECT * 1.0e6 );     // wait for slave to prepare for transfer
        SPDR = txData;                              // start transfer with Tx data
        while ( (SPSR & (1<<SPIF)) == 0 );          // wait for transfer to finish
        rxData = SPDR;                              // get Rx data
        SPI_SS_(PORT) = 1;                          // deselect slave
        _delay_us( WAIT_SLAVE_DESELECT * 1.0e6 );   // wait for slave to process Tx data

        if ( rxData != txData )                     // check Rx data integrity -- expect echo of previous Tx data
        {
            ERROR_LED_(PORT) = 0;
            // Extend SPI_SS_=1 width for scope trigger on pulse-width-greater-than non-error condition width
            _delay_us( 2.0 * WAIT_SLAVE_DESELECT * 1.0e6 );
            ERROR_LED_(PORT) = 1;
        }
    }
}

ATtiny84A USI Three-wire mode slave code:

#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <stdint.h>

// Echo received test data using slave USI in Three-wire mode, external clock
#define USICS0_VALUE    0       // clock source edge select (0 or 1): 0=="positive edge", 1=="negative edge"

// Test observations for USI slave (ATtiny84A @20MHz) in both external clock modes, USICS1=1 and USICS0=0/1
// with real SPI master (ATmega328P @16MHz) in modes 0/1/2/3 with Fusck = 1 MHz:
// SPI mode 0 (CPOL=0, CPHA=0): SCK idle  low; read MISO on SCK lead  (rise); write MOSI on SCK trail (fall) or half SCK cycle before 1st lead (rise); MOSI normally high (regardless of last bit)
// SPI mode 2 (CPOL=1, CPHA=0): SCK idle high; read MISO on SCK lead  (fall); write MOSI on SCK trail (rise) or half SCK cycle before 1st lead (rise); MOSI normally high (regardless of last bit)
// SPI mode 1 (CPOL=0, CPHA=1): SCK idle  low; read MISO on SCK trail (fall); write MOSI on SCK lead  (rise); MOSI normally same as last bit
// SPI mode 3 (CPOL=1, CPHA=1): SCK idle high; read MISO on SCK trail (rise); write MOSI on SCK lead  (fall); MOSI normally same as last bit

//  USI slave USICS0=0 / SPI master mode 0 (CPOL=0, CPHA=0):    DI=0x81 DO=0x03     (fail) "usitest_00.bmp"
//  USI slave USICS0=0 / SPI master mode 1 (CPOL=0, CPHA=1):    DI=0x81 DO=various  (fail) "usitest_01.bmp"
//  USI slave USICS0=0 / SPI master mode 2 (CPOL=1, CPHA=0):    DI=0x81 DO=various  (fail) "usitest_02.bmp"
//  USI slave USICS0=0 / SPI master mode 3 (CPOL=1, CPHA=1):    DI=0x81 DO=0x81     (pass) "usitest_03.bmp"

//  USI slave USICS0=1 / SPI master mode 0 (CPOL=0, CPHA=0):    DI=0x81 DO=various  (fail) "usitest_10.bmp"
//  USI slave USICS0=1 / SPI master mode 1 (CPOL=0, CPHA=1):    DI=0x81 DO=0x81     (pass) "usitest_11.bmp"
//  USI slave USICS0=1 / SPI master mode 2 (CPOL=1, CPHA=0):    DI=0x81 DO=0x03     (fail) "usitest_12.bmp"
//  USI slave USICS0=1 / SPI master mode 3 (CPOL=1, CPHA=1):    DI=0x81 DO=various  (fail) "usitest_13.bmp"

// Hardware abstraction for bit access:
struct bits
{
  uint8_t b0:1;
  uint8_t b1:1;
  uint8_t b2:1;
  uint8_t b3:1;
  uint8_t b4:1;
  uint8_t b5:1;
  uint8_t b6:1;
  uint8_t b7:1;
} __attribute__((__packed__));
#define BIT(portLetter, bitNumber, registerName) ((*(volatile struct bits*)&registerName##portLetter).b##bitNumber)
// portLetter = A-D, bitNumber = 0-7, registerName = "PORT", "PIN", or "DDR"
#define INPUT   0   // DDR bit = input
#define OUTPUT  1   // DDR bit = output

// ATtiny84A pin assignments
#define SPI_SS_(r)      BIT(A, 7, r)    // [Pin# 6] SPI slave select -- input from master
#define USI_DI(r)       BIT(A, 6, r)    // [Pin# 7] SPI MOSI -- input from master
#define USI_DO(r)       BIT(A, 5, r)    // [Pin# 8] SPI MISO -- output to master
#define USI_USCK(r)     BIT(A, 4, r)    // [Pin# 9] SPI SCK -- input from master 

int main(void)
{
    cli();

    SPI_SS_(DDR)    = INPUT;
    USI_DI(DDR)     = INPUT;
    USI_USCK(DDR)   = INPUT;
    USI_DO(DDR)     = OUTPUT;

    USICR = (1<<USIWM0) | (1<<USICS1) | (USICS0_VALUE<<USICS0); // USI mode = 3-wire; clock source = external

    while( 1 )
    {
        if ( SPI_SS_(PIN) == 1 )
        {
            USI_DO(DDR) = INPUT;                    // slave is deselected; float DO
            USISR = 1<<USIOIF;                      // synch/reset USCK edge counter, and clear overflow flag
            USIDR = USIBR;                          // pre-load Tx test data
        }
        else
        {
            USI_DO(DDR) = OUTPUT;                   // slave is deselected; drive DO (master waits enough time)
            if ( USISR & (1<<USIOIF) )              // transfer complete? (master supplies clock)
            {
                USISR = 1<<USIOIF;                  // reset USCK edge counter, and clear overflow flag
            }
        }
    }
}

I found what I believe is a spelling error in some of the atdf files for the atmega-2.0.12 device pack release.

$ grep "Referance" *.atdf
ATmega1608.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega1609.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega3208.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega3209.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega4808.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega4809.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega808.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">
ATmega809.atdf:        <register caption="Referance scale control" initval="0xFF" name="DACREF" offset="0x4" rw="RW" size="1">