Muliti layer Ice breaker

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Dear all
One of my customers has ordered a multilayer board for playing with spartan 6, it should be 8 layers PCB,

I have done a hundred very good quality two layer boards, But I still have fear getting the job, i want some Ice breaker tutorials or link from you! what rules should I follow? Do you recommend any good books, I know we have hundreds of them out there, But I have not that much time for searching among them,Also recently I have done some PCB's in china, the quality for two layers are very good,My customer needs a few boards, what 's you suggestion for prototyping the Giant BGA?

I love Digital
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Quote:
Giant BGA?

You mean FGG-900 package 31x31mm with 1mm pitch?
I have zero experience in routing something like that. Considering 8-layers and 900 pins involved that is enough to get lost in such mess even before opening a datasheet.

My first suggestion would be to properly take care of cooling of that beast. If you buy $partan 6 then you buy it to make it really hot. With part of heat dissipation down the PCB and 900 connections I guess the significant problem would be the local thermal expansion of a PCB underneath. Imagine what happens when surrounding PCB is at room temperature and such BGA heater (which also expands itself) is applied at one point in the middle of PCB.. Seems to me that even without external mechanical force the thermal expansion applies stress to PCB and can shear off some connections if not properly designed/cooled/heated. Now add to this an external mechanical stress..

Second thing is I would use a boundary scan and some pogo pins tool for test points because debugging the PCB design and looking for shorts/open circuits with multimeter is ok if you have 2-sided PCB and 400 soldering joints.
With 4000 soldering joints and 8-layer PCB prototype it may not be as pleasant..

No RSTDISBL, no fun!

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Make sure You spend the coin on bare board testing.

It costs a bit but You don't waste silicone on a dud board.
Dont crank the DRC to yhe absolute limits ( that is to say do not make the board track / space 0.004" just because the PCB company says it can do it. Make the design as agricultural as You can in order to enhance production yield. Talk to Your PCB shop and ask for their advice when it comes to pushing the envelope.

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Quote:
Make sure You spend the coin on bare board testing.

Do you mean electrical testing from PCB fab?
I would surely use electrical testing form PCB fab, And the Giant has 600 Pins, Do you recommend any design notes or any good and short appnote that would welcome new comers to the BGA land!?

I love Digital
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Ali_dehbidi wrote:
... spartan 6, it should be 8 layers PCB, ... Giant BGA?
No books and such but an EDA.
Some like Eremex (in Moscow) and TopoR (auto-router).
Eremex claims layer reduction and it eases BGA escape.
Eremex states that TopoR Lite runs under Wine on Linux.
Could try that version for a much smaller BGA as an evaluation of that tool.
Brutte wrote:
Seems to me that even without external mechanical force the thermal expansion applies stress to PCB and can shear off some connections if not properly designed/cooled/heated. Now add to this an external mechanical stress..
May consider underfill for production.
[url=http://www.embedded.com/design/s... revisited: How a decades-old technique enables smaller, more durable PCBs[/url] by Michael Yu and Syed Wasif Ali (Nexlogic Technologies) (embedded.com; January 27, 2011).
Brutte wrote:
Second thing is I would use a boundary scan and some pogo pins tool for test points because debugging the PCB design and ...
And debugging the VHDL or Verilog compiled for the FPGA.
So, add Xilinx ChipScope for code debug and a spare port (akin to use of a spare AVR 8-bit port to a logic analyzer).

"Dare to be naïve." - Buckminster Fuller

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Quote:
May consider underfill for production

Interesting idea. I have never seen such mounting. It seems this mainly prevents chip from falling off when subjected to acceleratons/vibrations. Article also points out that thermal cycling can influence mechanical properties.
Quote:
So, add Xilinx ChipScope for code debug

Are you suggesting toggling bits in software to verify the connections are ok? I thought JTAG boundary scan tools automate that process and there is no need for "toggling leds".

No RSTDISBL, no fun!

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That the FPGA's code is OK; this is used during the VHDL or Verilog test and debug during development.
FPGA simulators are used a lot during development but this FPGA's code will likely have some size so there'll likely be problems during the prototype test.
JTAG boundary scan could be used for production test (connections are OK).

"Dare to be naïve." - Buckminster Fuller

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If your customer just wants to play with a Spartan 6 (which is not really a high end FPGA, and I certainly wouldn't call it a beast; a Virtex 6 or 7 with 1500+ pins is what I call a beast) just tell him to buy a development kit from Xilinx. At least he knows the hardware is going to work without worry.

It is not trivial to design a PCB for these big BGA things. Have you thought about how you will get it actually soldered onto the board?

But what do yo want on the board? Just a bare FPGA with some voltage regulators and a JTAG connector? Bring out all remaining I/O pins to headers? Add a couple of DDR3 interfaces? The average toy peripherals you find on an a MCU devboard like LCDs, LEDs and button don't do justice to the phenomenal things the FPGA is capable of ;)

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jayjay1974 wrote:
It is not trivial to design a PCB for these big BGA things. Have you thought about how you will get it actually soldered onto the board?
A tech told me he reworks BGAs with a heat gun. :shock:
There are BGA-specific fluxes and rework machines (hot air, infrared).
The rework done on mobile phones has increased the demand and lowered the price of some BGA rework machines.
But, designing and fab'ing the PCB is not easy.
I've heard of internal power plane shorts inside multi-layer PCBs causing fires.

"Dare to be naïve." - Buckminster Fuller

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Even with special rework tools you still cannot inspect the solder joints without an (3D?) X-ray machine.

I wouldn't dare to solder on a really expensive FPGA with a heatgun :shock:

Eight layers limits the size of the FPGA you can use, or the maximum percentage of the available pins you can actually use. My guess about 256 to 384 pins, tops. Without more layers you just can't breakout the pins.

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And who said higher integration will mean simpler boards?

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jayjay1974 wrote:
Eight layers limits the size of the FPGA you can use, or the maximum percentage of the available pins you can actually use. My guess about 256 to 384 pins, tops. Without more layers you just can't breakout the pins.
The general formula is layers = (N/2)-2 for N is the largest of the number of rows or columns.
Texas Instruments created a BGA pin-out that reduced the number of layers by creating via run-out areas; larger package but reduced total cost.
Refs.
BGA escape via dimensions at 0.8mm pitch? (StackExchange).
EE Bookshelf: PCB Layout for BGA Packages (AN10778) (Adafruit Industries).

"Dare to be naïve." - Buckminster Fuller

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Actually, My friend do not want to Just play with the board, He has some custom hardware that he wanted to integrate to the PCB, And I have a friend how has a x-ray machine for inspecting the chip!, The main problem is me!
How I should melt my ice? What rules should I follow to design a good and reliable PCB, so that my friend will come back to me again! Do you recommend any good tutorial,appnote, etc...?

I love Digital
and you who involved in it!

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Xilinx documentation covers the recommended PCB layout guidelines, so gives information on vias, decoupling placement, board inductance etc. The rules for higher layer board counts are not too different from the lower counts. It's just you can get more tracks on the PCB with more layers to work with.

Get your head around layer stack ups. Ie which layers are signals and which are plane layers for GND and Power. The board will need to be symmetrical to prevent warping - a big issue with BGAs. Ie:

1 - Signal
2 - GND
3 - Signal
4 - Signal
5 - POWER
6 - Signal

The above is good because it is symmetrical about the centre of the board.

1 - Signal
2 - GND
3 - POWER
4 - Signal
5 - Signal
6 - Signal

The above is bad because the board will curve like a bananna!

Furthermore if you have a large amount of tracks on a layer, and the "opposite" layer has few, you should use copper thieving to balance the layers.

The thickness of the board will determine vias that you can use. The board house will have a aspect ratio between board thickness and minimum via size. You will also need to determine whether you need to use microvias, or conventional vias. Microvias are very small and can be placed "in pad", where as conventional vias must be placed to the side of the BGA pads. Microvias can only connect a couple of layers deep though - ie layer 1-3, so if you have a 20 layer board, you must use multiple vias to traverse layers 3 - 17.

A forest of vias under the BGA can make break out hard. Breaking out the BGA devices is the first thing that should be done. You should make sure your schematic is finished before breaking out as if you forget a signal which is in the middle of the BGA you may find it impossible to add it due to routing congestion, leaving you with not choice other than to rip all tracks up and break out again. Not fun!!!

The N/2 rules for layer count vs BGA array dimensions is a little far of the mark as many balls on these large devices are power.

Quote:
If your customer just wants to play with a Spartan 6 (which is not really a high end FPGA, and I certainly wouldn't call it a beast; a Virtex 6 or 7 with 1500+ pins is what I call a beast)

[Boasting]

My last project used the 1,925 pin Xilinx Virtex 7 2000T, which I managed to do on 20 layers - every single IO pin was used. (In fact there are two V7 2000T's and one V5 LX30T per board.) In total the project uses over 300 V7 2000T's and consumes some 22KW of power.

[/Boasting]

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What was the yield the board shop got?

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Don't know what the Fab shop got as I am somewhat removed from the manufacturing side, but Assy got > 97%,. That includes silicon failures, but then again this was pre-engineering silicon, so I can't complain. We did however sacrifice a couple of boards for thermal profiling prior to the main build - basically drilling holes all over the PCB and putting thermocouples in so we can accurately measure the temperature that the balls of the BGAs get to so we are sure that they reflow OK. Those were not included in the number above.

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Dear W0067814
Thanks for your advise, what was your track widths and clearances? Do you recommend anything on signal lengths for DDR3 interface as well? do you suggest a good layer stack up for 8 layers?

I love Digital
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DDR3 is am impedance controlled interface, so your trace widths will be determined by your board stackup geometry and the dielectric. It is best to choose your board house first, and then work with them to figure out the trace widths and clearances. We never calculate our own - we always as the board houses to specify them to us. Don't push the limits unless you have to. Thick traces are often better than thin ones. Less resistance and less inductance, though more capacitance. Thinner traces are more likely to reduce board yield. Low impedance signals such as DDR3's 50 Ohms will mandate thicker signals anyway. Higher impedance ones will mandate thinner signals.

Your stack up will be determined by things such as the number of plane layers you need (number of power supplies or power islands), trace density and the device pin density. - Ie: 0.4mm spacing BGAs require microvias as you don't have enough room for conventional vias between the pads. Microvias can only penetrate one or two layers, so you use microvias on the outer layers only and conventional vias on the core. This means to traverse from top layer to bottom layer, you may need to use 3 vias in series, depending on the design. (Micro - conventional core - micro)

DDR3 should be length matched quite tightly with in a byte lane - that is data related to the strobe. Each group should then be matched roughly to each other. 50 Ohms impedance termination to VCC/2. All traces to be over unbroken plane. Avoid vias if possible when working with high speeds. Avoid stubs. Avoid sharp corners on traces. On very high speed signals vias create stubs, so microvias can reduce this, or using the outer layers only on conventional vias.

An excellent book - expensive, but worth every penny - is "High Speed Digital Design: A Handbook of Black Magic" by Howard Johnson. His website is http://www.sigcon.com/. It's not specifically about PCB design, but more general high speed design so will be applicable to all future designs you undertake.

Take a look over some of the questions / answers he has published on there. Very interesting.
http://www.sigcon.com/Pubs/pubsA...

-Tim

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Thank you very much.

I love Digital
and you who involved in it!

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w0067814 wrote:
An excellent book - expensive, but worth every penny - is "High Speed Digital Design: A Handbook of Black Magic" by Howard Johnson. His website is http://www.sigcon.com/. It's not specifically about PCB design, but more general high speed design so will be applicable to all future designs you undertake.
Dr. Howard Johnson has an article on PCB design:
Fundamentals of PCB Design by Dr. Howard Johnson (TechOnline; Apr 2, 2010).

"Dare to be naïve." - Buckminster Fuller

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Quote:
Dr. Howard Johnson has an article on PCB design:
Fundamentals of PCB Design by Dr. Howard Johnson (TechOnline; Apr 2, 2010)

It said it has 50 minute duration,where can I find it?

I love Digital
and you who involved in it!

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Ali_dehbidi wrote:
Quote:
Dr. Howard Johnson has an article on PCB design:
Fundamentals of PCB Design by Dr. Howard Johnson (TechOnline; Apr 2, 2010)

It said it has 50 minute duration,where can I find it?

Hi ali!
i Thought here:

http://www.eetimes.com/Content/Courses/course3767/player.html

waiting till full load!

"One's value is inherent; money is not inherent"

 

Chuck, you are in my heart!

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Ali_dehbidi wrote:
Quote:
Dr. Howard Johnson has an article on PCB design:
Fundamentals of PCB Design by Dr. Howard Johnson (TechOnline; Apr 2, 2010)

It said it has 50 minute duration,where can I find it?
Under the View button (after log-in to UBM Tech); it's a Flash application.

"Dare to be naïve." - Buckminster Fuller

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w0067814 wrote:
The N/2 rules for layer count vs BGA array dimensions is a little far of the mark as many balls on these large devices are power.
Here's an example of layer reduction (from what the SoC manufacturer recommended):
A10-OLINUXINO FIRST PROTOTYPES ARE ASSEMBLING (Olimex)
Ref.
https://github.com/OLIMEX/OLINUXINO/tree/master/HARDWARE/A10-OLinuXino

"Dare to be naïve." - Buckminster Fuller