In one of the datasheets its said that the PLL can
generate up to 128MHz to supply hi resolution functions.
If I lock the PLL to an external clock, I can pull it
to 128MHZ it seems (after /4 I get 32MHz Clock for CPU).
But I can not lock it immediatly to more than aprrox
50MHz.
Any help/infos ?
What speed is your external clock?
But I can not lock it immediatly to more than aprrox
50MHz.
Setup is as follows: The external clock input XTAL1
is enabled. A signalgenerator with variable frequency
(1MHZ..10MHz) is attached to XTAL1.
If I select this clock as system clock that seems
to work.
Now I use this clock as reference for the PLL.
I use N=16 a PLL divider, so the PLL should lock
to 16x external clock.
I enable the /2 dividers between PLL and systemClock
so that the CPU should be clocked by PLL/4.
If I use 2MHz as input the PLL will lock to 32MHz
and the CPU works at 8MHz, that works fine.
If I slowly increase PLLref frequency
from 2MHz to 4MHz the CPU clock will increase
accordingly to 16Mhz. The PLL stays locked
at 16*4=64MHz .
If I then reset the CPU the PLL will not lock again.
I somewhere read, that the PL would work up to
128MHz.
Its just playing around and ge knowledge what I
can do with the PLL.
Ok, so the setup works if you slowly increase the reference frequency to 4 MHz. But it doesn't work if you start up directly at 4 MHz.
This could have something to do with the clock setup sequence. Something with timing, I guess. The board I'm currently working on has a 4 MHz crystal. I multiply the crystal clock with 15, and then divide it by 2 to get 30 MHz. Multiplying with 16 works fine as well.
This is the code I use:
OSC_XOSCCTRL=0x4B; // Set xtal freq rng 2-9 MHz; select ext xtal, startup 16K clk OSC_CTRL|=0x08; // Enable ext oscillator while (!(OSC_STATUS & 0x08)); // Wait until ext oscillator ready OSC_PLLCTRL=0xCF; // Select ext osc as PLL source; multiply factor 15 CCP=0xD8; // Disable protection CLK_PSCTRL=0x01; // Set clock prescaler A to 2 OSC_CTRL|=0x10; // Enable PLL while (!(OSC_STATUS & 0x10)); // Wait until PLL ready CCP=0xD8; // Disable protection CLK_CTRL=0x04; // Set PLL as system clock source
You can compare this with your own clock setup code. Remember the wait loops to ensure the clocks are stable before you start using them.
Br, E
It sounds like your sig gen might be the issue. Try using say a 4MHz crystal. I use a 16MHz crystal doubled up to 32MHz without any problems.
@ErikT
Thanks for your routine. It worked immediately
and showed what I made wrong: I changed the
pre-dividers in CLK_PSCTRL after having switched to
PLL clock. That seemed to "kill" the CPU-clock.
Now I do it before switching to the PLL clock
and everything works as expected!
:)
