Really appreciate any help that can be offered here - this is driving me crazy.
I'm using Timer0 on an ATMega328, trying to set it up for OCRa interrupt on match, and with auto-clear via CTC. So it should count to 4, reset to 0 via CTC, and generate a match interrupt.
Loading it on a processor, it gave indications of RESET, as I had some I/O strobes that have been taken out just to simplify the code.
So I'm running it on the simulator, and that also does a bizarre thing at the CTC match time (counter = 4).... just suddenly moves the PC and starts executing code again a few lines into the program! Never hits any of the vectors, just changes the PC and Stack-ptr.
If any of the experts on this board have time to look at it, I would really appreciate it.... short and sweet.... pasted below and enclosed.
==================================================== .include "m328Pdef.inc" ;standard processor definitions for ATMega328 .def tempr1 =r24 ;Scratchpad register .cseg .org 0 RESET: ;******* VECTOR TABLE ****** RJMP INIT ;Reset RETI ;Int0 RETI ;Int1 RETI ;PCint0 RETI ;PCint1 RETI ;PCint2 RETI ;WDT RETI ;Timer2_CmpA RETI ;Timer2_CmpB RETI ;Timer2_Ovflow RETI ;Timer1_Capt RETI ;Timer1_CmpA RETI ;Timer1_CmpB RETI ;Timer1_Ovflow RJMP Timer0_OCRa ;Timer0_CmpA RETI ;Timer0_CmpB RETI ;Timer0_Ovflow RETI ;SPI, STC RETI ;USART Rx RETI ;USART UDRE RETI ;USART Tx RETI ;ADC done RETI ;EEPROM done INIT: LDI tempr1,low(RAMEND) ;Initialize the Stack Ptr OUT SPL,tempr1 LDI tempr1,high(RAMEND) OUT SPH,tempr1 ; Timer0 setup LDI tempr1,1<<CS01 ;Prescaler = /8 (8mhzXTAL / 8 = 1mhz) OUT TCCR0B,tempr1 LDI tempr1,0 ;Initialize Timer register OUT TCNT0,tempr1 LDI tempr1,4 ;Initialize OCR0a for the match OUT OCR0A,tempr1 LDI tempr1,1<<WGM01 ;Set WGM1 to a '1' to set Clear-Timer-on-Compare (CTC) mode OUT TCCR0A, tempr1 LDI tempr1,1<<OCIE0A ;Interrupts enabled on OCR0a matches STS TIMSK0,tempr1 SEI ;Enable irq's background: RJMP background ;Just loop here waiting on Timer0 OCRa ; Timer0 - OCR0a irq Timer0_OCRa: RETI
$ Fixed code tags - JS $