This is the tale of a (now solved) subtle bug in a 5v to 3v3 level converter; it might help someone with a similar issue. In this case I was talking to some Ramtron FRAM.
Recall that for my design work I need to use minimum power, and I need to run at temperatures in excess of 150C. The first point implies that, for example, resistive dividers are not a permissible way of making the 5-3.3 conversion, and the second means that without six hundred hours of testing, I can only use components we've already used and know work on the tool.
I need to drive four lines: three from the five volt side, and one from the 3v3 side; it's being bit-banged from a pic.
The 3v3 to 5v side is easy; the standard BSN20 fet with the gate pulled up to the 3v3 rail and 4k7 on either side of it to the appropriate rail. This works well (and actually, I can probably remove the pull-up on the 3v3 side since its a totem-pole output on the driver). The other way around isn't so neat...
Thought one: diodes pointing to the 5v side, with pullups (3k3) on the 3v3 side. Unfortunately, they took the ground to only about 0.85v - a combination of the 220 ohm safety resistors on the pic's inputs and the band-gap voltage. Also, he input signal spiked up to 5v for perhaps a hundred ns before dropping to 3v3... and the memory check failed approximately 50% of the time. Damn.
Thought two: schottkys. Better; the zero is now down to under 250mV but the rise time on the 3v3 side is appalling; about a microsecond. Changed the pullups to 1k5 but it's still a half microsecond rise time. Plus, schottkys are leaky at high temperature. Nonetheless, let's try it: nah. Getting memory read or write errors about one in ten thousand or so... too many.
Thought three: the FET approach is bidirectional... yep, it's bidirectional but it's still got a slow rise time on the 3v3 side (because the fet is actually turning off and relying on the pullup). It's better than the schottky, but not by much; the rise time is about 400ns. Errors are now down to about one in a million - still not good enough.
Thought four: buffer the signal. It's actually the clock signal to the chips that's the issue. The steering logic is fine with its slow rise time, but the FRAM isn't; it was missing the clock every now and then, and with an SPI interface that means either that the command/address doesn't get through, or that you read or write offset from the start of the byte. This appears to work; I managed about two million cycles of memory test yesterday afternoon, at temperature, without error. (I know the chips are capable of at least two hundred million cycles from previous testing).
I need to decide today whether to go for this design, or whether to start again: I've located a 74LCX series chip that's rated to 125 and will probably work at 150 (needs testing, though) and which has 5v tolerant inputs. Alternatively, if I can persuade the boss, use 3v3 throughout this block... that moves the level conversion issues to his bit!