Atmega128 ADC - Sampling Frequency.

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I have atmega128A connected to external 16MHz crystal.
I am trying to check maximum ADC samples it can support. After reading datasheet and other posts on forum I want to post my results for better understanding.
My configuration is..
1. External Crystal 16 MHz
2. Adc prescalar = 32 (which give 500K, out of range as per datasheet..but it works.)
3. UART connected to PC having baud rate 115.2K.
4. I have given 500 Hz sine wave input to ADC channel 0. I am getting mostly 16-20 samples per sine wave (per 500 Hz) that means 8 to 10K samples per second.

I want to know that can I say that above configuration will give me atleast 8K samples per second. Or I am missing something....

I am attaching image of sine wave obtained at my PC.

Attachment(s): 

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The problem with running the prescaler a little too fast is: the sample period is 1.5 clocks, so if the new sample is too far away from the old sample, it doesn't have time to slew there, and the sample is too small. This would be evident when reading 8 channels with even channels with a lo voltage and odd channels at a hi voltage. While chasing a sine wave, the sampling phenomenon is harder to see.

Imagecraft compiler user

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hey Bob! Thanks for answering.
I knew that prescalar is little higher, but thought let see what happens. Here, I am not able to figure out the conclusion as resulting sine wave looks ok.
So, do u agree with total no. of samples/sec. is around 8k?
If one needs to use single channel of ADC, is it advisable to go with above config. with same prescalar?

Thanks.

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Quote:
I am getting mostly 16-20 samples per sine wave
At 500k ADC clocks per second and continuous reading you should be getting ~38k samples per second (13 ADC clocks per sample).
Quote:
out of range as per datasheet..but it works.
But it does not give you 10 bits per sample.

Regards,
Steve A.

The Board helps those that help themselves.

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Your test does not mean very much because of the way in which the ADC "fails". It does not stop operating. It simply starts to loose resolution, least significant bits, first. Your waveform reconstruction mostly shows what the most significant bits are doing.

It also does not behave like a classic single pole system. The nature of the degradation as the input frequency increases is not characterized by reduced data amplitude.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Quote:

At 500k ADC clocks per second and continuous reading you should be getting ~38k samples per second (13 ADC clocks per sample).

Hey Steve! Correct me if I am wrong. My program has other stuff in one iteration of continuous loop along with ADC read...May be the reason for reduction of samples to 8K from 38K?
Quote:

Your test does not mean very much because of the way in which the ADC "fails". It does not stop operating. It simply starts to loose resolution, least significant bits, first. Your waveform reconstruction mostly shows what the most significant bits are doing

Hello Jim! Is it ok to use this if somebody wants 8 bit resolution. My results shown here are 8 bits only.

Thanks to all.

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You can go quite a bit higher (than the spec) and get 8 reliable bits. Someone did an excellent test on ADC resolution vs clock rate a while back. I don't remember the numbers but yours looks consistent.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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For only 8-bit result I've been using 1MHz ADC clock with good results.
OTOH I take 16 samples in a row on each channel and use average of that (slowly changing signal).

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one thing I don't understand that if you observe the image posted above, you found that more sampling point at both peak of sine wave...and it consistent with other frequencies...Is this related to sample/hold circuit of ADC?