AVR Freaks

In my nixies I used to experimentally find out good pulse width which would be just enough not to saturate the inductor and stick with it. Changing duty cycle is not a very good method of control in my experience, simple ON/OFF works better. Any deviation from the optimal duty cycle/frequency may cause heating or dramatic lost of efficiency. Did you try to change the drive frequency? 250kHz sounds like a lot of kHz for a 250µH inductor.

The transistor and the inductor should stay a little bit warm, but only a little bit.

@Giorgos, Jim: I compared the characteristics of STD14NM50N and my good for everything n-MOSFET of choice, IRF630N, they appear to be in the same ballpark.

This in my mind registers as 5V AVR-drivable MOSFET. Are there other parameters one should take care about?

Svo, I am sorry but I thought that you were already using MOSFET drivers, since it is obvious that these IRFxxx FETs are too old to be logic level ones. Anyway, this is the reason why they overheat when their load is raised: Because they are not being driven adequately and their Rds_on never reaches the advertised levels. I'll try to explain that but it might get long... So, please, bear with me.

Speaking before of the Miller plateau region voltage visualisation, let me correct a mistake: I used the rather beefy NTD60N02R (25V, 62A, 8.4mΩ) with Vgs_th=2.0V, Qg=9nC, and Vgs_Miller=3.0V (not 4.1V, I wrote above), so it could be driven by a 5.0V AVR I/O: 5.0V-0.7V > 3.0V.

The transfer characteristics of a MOSFET are based on the charge quantity accumulated to the Gate capacitance, in order to "open" the Channel and start the Drain current flowing; and vice versa, based on the charge quantity removed from the Gate capacitance in order for the Channel to "close" and stop the Drain current flow.

Now, the Gate capacitance is not as simple as it sounds to be. There are three distinct capacitances in the device: The Cgs (the Gate-to-Source capacitance), the Cds (the Drain-to-Source one) and, the most important of them all, the Cgd (the Gate-to-Drain capacitance). The data sheets define them as follows, since this way the capacitances can be directly measured:
1. The Input Capacitance: Ciss = Cgs + Cgd
2. The Output Capacitance: Coss = Cds + Cgd
3. The Reverse Transfer Capacitance: Crss = Cgd

Only the capacitance Cgs is linear; Cgd and Cds are voltage depended. Additionally, the Gate-to-Drain capacitance (Cgd) is the most important parameter of them all because it is the main feedback element between the input and the output of the device. It is the capacitance charged with high voltage (Vdg = Vds-Vgs) charges that actively resist any Vgs level change. It is known as the Miller Capacitance.

Another important set of parameters given at the data sheets is the Gate Charge Qg that is also broken down in the distinct charges of Qgs and Qgd, where Qg = Qgs + Qgd and it is the minimum charge required to switch the device on. Defining the gate element charges helps calculations; for example, a 10nC charge can be moved to Cgs in 10msec time by applying a Gate current of 1mA, or in 5μsec if the Gate current becomes 2A. We also know that Q=C*V, I=C*(dv/dt), etc., so knowing the charge and the capacitance values we can easily calculate the current, voltage and timing elements needed for the Gate drivers.

There is a common misconception about the MOSFET parameter called Threshold Voltage (Vgs_th) because many people think that the moment Vgs becomes equal to Vgs_th, the MOSFET becomes fully conductive. This is wrong! When Vgs becomes equal to Vgs_th, the MOSFET begins to conduct, with its Id just becoming measurable (250μA at 25°C, typically)! From this point there is a long way until the device becomes fully conductive and decrease its Rds_on to the levels that will allow the advertised maximum current to flow. So, Vgs_th is just another parameter and not as critical as Vgs_Miller (the Miller plateau region voltage).

A MOSFET responds instantaneously to changes in Gate voltage Vgs. There are four Vgs regions during the device turn-on period and the goal is to raise Vgs to the final value (Vdriver) as fast as possible:
1. 0V <= Vgs < Vgs_th: The FET is off, while Vgs is charging Cgs. This is called turn-on delay.
2. Vgs_th <= Vgs < Vgs_Miller: The device begins to conduct. This is the FET linear region, when Id is proportional to Vgs and Vds has not changed yet from Vds_off, and Id = g*(Vgs-Vgs_th), so Vgs_Miller = Vgs_th + (Id/g).
3. Vgs = Vgs_Miller: This is the Miller plateau region of Vgs, where Vgs remains constant until the gate driver has discharged Cgd while Id remains constant, and Vds will start to fall.
4. Vgs_Miller < Vgs <= Vdriver: This is the last step of the FET turn-on, where Cgs and Cgd have been charged to the final point, and the final value of Vgs now defines Rds_on and thus Vds. (Thus the NTD60N02R parametric Rds_on characterisation: "Rds_on=11.2mΩ for Vgs=4.5V and Rds_on=8.2mΩ for Vgs=10V")

The turn-off procedure is a backtracking of the turn-on steps, above. The goal here is the same: To turn the device off as soon as possible. Again, to turn the device completely off will need to completely discharge Cgs by pulling Vgs to Vss, while the hardest part will again be the Miller effect, where Cgd will oppose any Vgs change, trying to keep Vgs at the Miller plateau voltage region.

-George

Since a Vgs swing of 10V at 10ns time is considered to be an excellent gate switch I think that you are more than good.

Have you checked for any excessive ringing at the Drain? That would mean that the inductor and/or the PCB have high parasitic inductance that would need a snubber to dump the transients that could violate any of the FET's parameters; but that FET has a 550V Vds... If, again, you were running the modulator too fast, you could not saturate the inductor; you would just not charge it with enough energy to return back to the load.
Right now, I cannot think of something else.

-George

EDIT: Oops... Mike, I think you are right. And, thank you!
Michael, I am sorry for hijacking the thread... Would you like me to move the irrelevant message?

Well, inductor temperature rise comes from only one thing: losses.

There are two significant losses. One is the wire resistance. This gives you heating proportional to the average current. The other is core, generally due to saturation. Saturation always happens at ripple peaks because the nonlinearity is instantaneous, rather than average.

Be careful when you measure current, especially at 250KHz. A good indicator of core behavior is to measure the voltage across the inductor. You need two well-matched probes and a scope that is capable of proper differential operation. One probe at each end of the inductor; subtract the load-side voltage from the source-side voltage. If the core is saturating, you will not see a triangle or exponential type waveform. Instead, the slope will increase at the high-current peaks (the peaks will look "sharper" than they should be).

One of the things you have NOT said is how this behaves with load. Do the inductor and the FET stay hot at light load and get hotter as the load increases? Or, are they always hot, no matter what the load?

I would like to see waveforms for the voltages at all three FET terminals and across the load. Without these, we are pretty much shooting in the dark.

Jim

Another thing that is likely happening here is that the saturation current drops as the core heats up. That is, it takes less current to saturate. It is related to the Curie Temperature of the core material. It turns into a positive feedback mechanism.

Core or coil heating warms the core. Saturation current drops. Core starts to saturate at ripple peaks, even if it was not saturating at the start. Additional heating occurs, dropping the saturation current more, resulting in more heating. Etc.

Jim