AVR Freaks

Michael, I will insist on the second argument Jim made, above, about the fast charge/discharge of the Gate.

What are you driving the FET Gate with? I am afraid that a bare AVR I/O is inadequate to drive that FET. Though the Gate threshold voltage is stated to be <4V, at the figure 13 of the data sheets is shown that Vgs should be no less than 5.5V approximately (that is the Miller plateau). With a Vgs value lower than that, the FET will never reach the advertised Rds_on levels.

To add in salt to injury, the Gate driver should be able to deliver enough current (~1A or more) in order to charge/discharge the total Gate capacitance fast enough; especially when dialing with high Drain voltages, where the Miller effect becomes a considerable factor.

I believe that if you probe the Gate voltage you will be able to see the Miller plateau on the oscilloscope screen during both the phases of charge and discharge, instead of seeing a crisp square wave at the Gate; and that plateau will surprisingly disappear when you probe the Gate again, with the HV load disconnected. It happened to me recently, when a 5.0V t861 high speed PWM I/O was driving directly a FET whose Miller plateau was at 4.1V while the Drain load voltage was less than 25V. You should try that little experiment yourself!

Now, if you have the drive voltage, it will become easy to amplify the drive current by using an inexpensive complementary emitter-follower driver stage, using the BC337/BC327 or BC639/BC640 transistor pairs for example; keep in mind though that this current driver will also decrease the drive voltage by 700mV.

-George

Since a Vgs swing of 10V at 10ns time is considered to be an excellent gate switch I think that you are more than good.

Have you checked for any excessive ringing at the Drain? That would mean that the inductor and/or the PCB have high parasitic inductance that would need a snubber to dump the transients that could violate any of the FET's parameters; but that FET has a 550V Vds... If, again, you were running the modulator too fast, you could not saturate the inductor; you would just not charge it with enough energy to return back to the load.
Right now, I cannot think of something else.

-George

EDIT: Oops... Mike, I think you are right. And, thank you!
Michael, I am sorry for hijacking the thread... Would you like me to move the irrelevant message?

Your inductor doesn't charge the capacitor at all unless it exceeds the voltages currently on it. I see that in your lower trace - it just isn't making it. If it did, the peaks would have a flat top. All the energy, therefore, is being dissipated in the FET. The second peak does look like ringing, but I can hardly imagine you have enough stray capacitance on the drain for that sort of time constant. More likely the FET is turning on again, possibly the body diode is avalanching, and the second peak is a second turnoff. If you connected the top of the coil to 12V you would expect to see 0V with the FET on, a high peak when it turns off and then a steady 12V during the rest of the off period. I don't see the steady 12V anywhere.

D'oh - you have the drain trace AC coupled, that's why there's no 12V. I bet a lot of other relevant detail is also lost. I could probably tell you a lot more if I could see it DC coupled.

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You can use the inductor's own coil resistance as a current sensor. Just measure the resistance of the coil, and as stated above measure the differential voltage between both ends of the inductor. Mr. Ohm will do the rest for you.

Nice joke.
When the inductor current increases, it has across it 12V - Mosfet voltage drop. When the current decrease, it has 220 - 12V. After this, if it is working in discontinuous mode will self oscillate.
Some other people claim to measure the current through Mosfet measuring the drena-source voltage, assuming a known resistance. Just theories, since the drena - source voltage when off is too high to allow a voltmeter or scope to accurately measure it.
Best way is the old way: put a series resistor between "-" and source and measure it, see it on the scope. Sure, with any comfort comes the price: extra loses on the resistor. Do not use a wound resistor.
Any decent power supply has some means for over currents. The boost topology is evil if you "forget" the transistor ON.
Me, I would use one of the hundreds of specialized chips for this purpose.

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The problem is that the drain of my FET, once Vgs is brought low, often won't make it high enough to charge the output capacitors. Like there is a large delay from when the FET turns off to when the drain swings high, and by that time often the FET is already being turned on again so the drain falls down immediately. During the part of the output triangle wave where the output is dropping slowly, the drain *never* makes it high enough to charge the output capacitor. During the part of the triangle waveform where the output is increasing, the drain makes it high enough to charge the output capacitors about once every other cycle (so about at 125KHz).

It looks the loop regulation is not working well. When you see the drain voltage is not reaching 220V, this means the micro has reduced the PWM duty cycle because is sees enough voltage on the capacitors. Your loop regulation is too simple. Use at least a true proportional regulation and make it faster than the output voltage oscillate. Or even add the derivative component to the loop. It will eat a good chunk of the CPU time. Another way is to increase the output capacitors. Check the ADC accuracy and all your math in the loop regulation also.
I am not sure I understand your scope pictures, for how long time the transistor is ON on the first picture ?
And ah, I should have start with saying that the transistor used is way to big comparing the inductor. Much of the work the inductor has to do is to charge and discharge the transistors capacitance. That transistor is fit for hundreds watts power supply.
George.