Strange problem with 220V boost converter

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Hi - I have a boost converter controlled by an AVR that is having some problems.

Specifically, it's running hot. Very hot (almost to the point of not being touchable). Both the FET and the inductor get toasty. Load is about 16ma @ 220V. I have not measured the input current (which is at 12V) but I imagine my efficiency is terrible. I will try to test this soon, however.

The output looks like a triangle waveform where the ramp up is very steep and the ramp down slope is maybe a 20th of the magnitude of the ramp up. Frequency is about 30Hz. Peak to peak is about 5V.

My PWM speed is 250KHz, my control loop speed is 2KHz and is trivially simple - if the measured output is too high it reduces the duty cycle by one step, and if it is too low it increases it by one step.

The problem is that the drain of my FET, once Vgs is brought low, often won't make it high enough to charge the output capacitors. Like there is a large delay from when the FET turns off to when the drain swings high, and by that time often the FET is already being turned on again so the drain falls down immediately. During the part of the output triangle wave where the output is dropping slowly, the drain *never* makes it high enough to charge the output capacitor. During the part of the triangle waveform where the output is increasing, the drain makes it high enough to charge the output capacitors about once every other cycle (so about at 125KHz).

The main parts are:

Switch: ST STD14NM50N
Inductor: Bourns SRR1280-271K (270uh)
Diode: Diodes Inc ES1G-13-F
Output capacitors: 1x Panasonic EEU-ED2E220 (22uf electrolytic)
2x TDK C3216X7T2W104K (100nf ceramic)

Gate is driven by a self designed FET gate driver, and rise and fall times are under 25ns.

Anybody have a clue as to what is going on here? I haven't had any good ideas yet.

Thanks!!

Last Edited: Mon. Apr 9, 2012 - 05:46 AM
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Hot inductor almost always means saturation. That is, in turn, killing your FET.

Use an inductor with a higher saturation current.

It also sounds like you are not driving the gate adequately. Sometimes, the peak current has to be an amp or more. If the gate voltage is slow to change, you are not delivering gate charge fast enough.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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ka7ehk wrote:
Hot inductor almost always means saturation. That is, in turn, killing your FET.

Use an inductor with a higher saturation current.

Jim


Hi Jim - thanks for the input. Funny thing is - I should be well under the saturation current of my inductor. My calculations showed a DC current of under 400ma [a rough calculation would be: (20ma * 220V / 12V]) with a ripple of about 200ma. I've verified this with a simulation, as well. The saturation current of my inductor is 1.6A. That doesn't mean I'm not saturating - I suspect I am (being that I don't seem to be dumping any power into the output capacitors for long periods of time) - but I don't know why this is happening.

I did not design in to the PCB a nice way of measuring the current of the inductor but that is on my list of things to try to hack on.

I will try to post scope plots tomorrow.

Also, I should mention that I edited my original post to reflect that my output voltage is ~220V, not 300V.

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Michael, I will insist on the second argument Jim made, above, about the fast charge/discharge of the Gate.

What are you driving the FET Gate with? I am afraid that a bare AVR I/O is inadequate to drive that FET. Though the Gate threshold voltage is stated to be <4V, at the figure 13 of the data sheets is shown that Vgs should be no less than 5.5V approximately (that is the Miller plateau). With a Vgs value lower than that, the FET will never reach the advertised Rds_on levels.

To add in salt to injury, the Gate driver should be able to deliver enough current (~1A or more) in order to charge/discharge the total Gate capacitance fast enough; especially when dialing with high Drain voltages, where the Miller effect becomes a considerable factor.

I believe that if you probe the Gate voltage you will be able to see the Miller plateau on the oscilloscope screen during both the phases of charge and discharge, instead of seeing a crisp square wave at the Gate; and that plateau will surprisingly disappear when you probe the Gate again, with the HV load disconnected. It happened to me recently, when a 5.0V t861 high speed PWM I/O was driving directly a FET whose Miller plateau was at 4.1V while the Drain load voltage was less than 25V. You should try that little experiment yourself!

Now, if you have the drive voltage, it will become easy to amplify the drive current by using an inexpensive complementary emitter-follower driver stage, using the BC337/BC327 or BC639/BC640 transistor pairs for example; keep in mind though that this current driver will also decrease the drive voltage by 700mV.

-George

I hope for nothing; I fear nothing; I am free. (Nikos Kazantzakis)

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In my nixies I used to experimentally find out good pulse width which would be just enough not to saturate the inductor and stick with it. Changing duty cycle is not a very good method of control in my experience, simple ON/OFF works better. Any deviation from the optimal duty cycle/frequency may cause heating or dramatic lost of efficiency. Did you try to change the drive frequency? 250kHz sounds like a lot of kHz for a 250µH inductor.

The transistor and the inductor should stay a little bit warm, but only a little bit.

@Giorgos, Jim: I compared the characteristics of STD14NM50N and my good for everything n-MOSFET of choice, IRF630N, they appear to be in the same ballpark.

                                    STD14NM50N  IRF630N
Input capacitance:                  816pF       575pF
Gate total charge/to source/miller: 27/4.6/15   35/6.5/17
Gate threshold:                     2-3-4       2-x-4

This in my mind registers as 5V AVR-drivable MOSFET. Are there other parameters one should take care about?

The Dark Boxes are coming.

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Max current, RDs[ON] and The curve which shows max Ids at particular gate voltages.

Usually you would want to drive the gate with at a lot more voltage than the Threshold is rated for.

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Svo, I am sorry but I thought that you were already using MOSFET drivers, since it is obvious that these IRFxxx FETs are too old to be logic level ones. Anyway, this is the reason why they overheat when their load is raised: Because they are not being driven adequately and their Rds_on never reaches the advertised levels. I'll try to explain that but it might get long... So, please, bear with me.

Speaking before of the Miller plateau region voltage visualisation, let me correct a mistake: I used the rather beefy NTD60N02R (25V, 62A, 8.4mΩ) with Vgs_th=2.0V, Qg=9nC, and Vgs_Miller=3.0V (not 4.1V, I wrote above), so it could be driven by a 5.0V AVR I/O: 5.0V-0.7V > 3.0V.

The transfer characteristics of a MOSFET are based on the charge quantity accumulated to the Gate capacitance, in order to "open" the Channel and start the Drain current flowing; and vice versa, based on the charge quantity removed from the Gate capacitance in order for the Channel to "close" and stop the Drain current flow.

Now, the Gate capacitance is not as simple as it sounds to be. There are three distinct capacitances in the device: The Cgs (the Gate-to-Source capacitance), the Cds (the Drain-to-Source one) and, the most important of them all, the Cgd (the Gate-to-Drain capacitance). The data sheets define them as follows, since this way the capacitances can be directly measured:
1. The Input Capacitance: Ciss = Cgs + Cgd
2. The Output Capacitance: Coss = Cds + Cgd
3. The Reverse Transfer Capacitance: Crss = Cgd

Only the capacitance Cgs is linear; Cgd and Cds are voltage depended. Additionally, the Gate-to-Drain capacitance (Cgd) is the most important parameter of them all because it is the main feedback element between the input and the output of the device. It is the capacitance charged with high voltage (Vdg = Vds-Vgs) charges that actively resist any Vgs level change. It is known as the Miller Capacitance.

Another important set of parameters given at the data sheets is the Gate Charge Qg that is also broken down in the distinct charges of Qgs and Qgd, where Qg = Qgs + Qgd and it is the minimum charge required to switch the device on. Defining the gate element charges helps calculations; for example, a 10nC charge can be moved to Cgs in 10msec time by applying a Gate current of 1mA, or in 5μsec if the Gate current becomes 2A. We also know that Q=C*V, I=C*(dv/dt), etc., so knowing the charge and the capacitance values we can easily calculate the current, voltage and timing elements needed for the Gate drivers.

There is a common misconception about the MOSFET parameter called Threshold Voltage (Vgs_th) because many people think that the moment Vgs becomes equal to Vgs_th, the MOSFET becomes fully conductive. This is wrong! When Vgs becomes equal to Vgs_th, the MOSFET begins to conduct, with its Id just becoming measurable (250μA at 25°C, typically)! From this point there is a long way until the device becomes fully conductive and decrease its Rds_on to the levels that will allow the advertised maximum current to flow. So, Vgs_th is just another parameter and not as critical as Vgs_Miller (the Miller plateau region voltage).

A MOSFET responds instantaneously to changes in Gate voltage Vgs. There are four Vgs regions during the device turn-on period and the goal is to raise Vgs to the final value (Vdriver) as fast as possible:
1. 0V <= Vgs < Vgs_th: The FET is off, while Vgs is charging Cgs. This is called turn-on delay.
2. Vgs_th <= Vgs < Vgs_Miller: The device begins to conduct. This is the FET linear region, when Id is proportional to Vgs and Vds has not changed yet from Vds_off, and Id = g*(Vgs-Vgs_th), so Vgs_Miller = Vgs_th + (Id/g).
3. Vgs = Vgs_Miller: This is the Miller plateau region of Vgs, where Vgs remains constant until the gate driver has discharged Cgd while Id remains constant, and Vds will start to fall.
4. Vgs_Miller < Vgs <= Vdriver: This is the last step of the FET turn-on, where Cgs and Cgd have been charged to the final point, and the final value of Vgs now defines Rds_on and thus Vds. (Thus the NTD60N02R parametric Rds_on characterisation: "Rds_on=11.2mΩ for Vgs=4.5V and Rds_on=8.2mΩ for Vgs=10V")

The turn-off procedure is a backtracking of the turn-on steps, above. The goal here is the same: To turn the device off as soon as possible. Again, to turn the device completely off will need to completely discharge Cgs by pulling Vgs to Vss, while the hardest part will again be the Miller effect, where Cgd will oppose any Vgs change, trying to keep Vgs at the Miller plateau voltage region.

-George

I hope for nothing; I fear nothing; I am free. (Nikos Kazantzakis)

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Giorgos_K wrote:
Michael, I will insist on the second argument Jim made, above, about the fast charge/discharge of the Gate.

What are you driving the FET Gate with? I am afraid that a bare AVR I/O is inadequate to drive that FET. Though the Gate threshold voltage is stated to be <4V, at the figure 13 of the data sheets is shown that Vgs should be no less than 5.5V approximately (that is the Miller plateau). With a Vgs value lower than that, the FET will never reach the advertised Rds_on levels.

To add in salt to injury, the Gate driver should be able to deliver enough current (~1A or more) in order to charge/discharge the total Gate capacitance fast enough; especially when dialing with high Drain voltages, where the Miller effect becomes a considerable factor.

I believe that if you probe the Gate voltage you will be able to see the Miller plateau on the oscilloscope screen during both the phases of charge and discharge, instead of seeing a crisp square wave at the Gate; and that plateau will surprisingly disappear when you probe the Gate again, with the HV load disconnected. It happened to me recently, when a 5.0V t861 high speed PWM I/O was driving directly a FET whose Miller plateau was at 4.1V while the Drain load voltage was less than 25V. You should try that little experiment yourself!

Now, if you have the drive voltage, it will become easy to amplify the drive current by using an inexpensive complementary emitter-follower driver stage, using the BC337/BC327 or BC639/BC640 transistor pairs for example; keep in mind though that this current driver will also decrease the drive voltage by 700mV.

-George


Hi George - the main FET's gate is driven with a full +12V swing by a self designed gate driver. I've verified that rise time on the gate is under 25ns (under load) and fall time is even less. I think that is sufficient, don't you?

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svofski wrote:
In my nixies I used to experimentally find out good pulse width which would be just enough not to saturate the inductor and stick with it. Changing duty cycle is not a very good method of control in my experience, simple ON/OFF works better. Any deviation from the optimal duty cycle/frequency may cause heating or dramatic lost of efficiency. Did you try to change the drive frequency? 250kHz sounds like a lot of kHz for a 250µH inductor.

The transistor and the inductor should stay a little bit warm, but only a little bit.

@Giorgos, Jim: I compared the characteristics of STD14NM50N and my good for everything n-MOSFET of choice, IRF630N, they appear to be in the same ballpark.

                                    STD14NM50N  IRF630N
Input capacitance:                  816pF       575pF
Gate total charge/to source/miller: 27/4.6/15   35/6.5/17
Gate threshold:                     2-3-4       2-x-4

This in my mind registers as 5V AVR-drivable MOSFET. Are there other parameters one should take care about?


Hi svofski - slowing down the drive frequency is among the first things I'm planning on trying today :) The reason for the fast drive frequency vs large inductance is that I want my boost converter to remain in continuous mode for maximum efficiency. Of course, whatever mode it is in right now is clearly about as inefficient as modes come!

I will mention that I have one major concern with how I am adjusting the duty cycle - that during start up, I could blow out my inductor. I already have a soft start function (that I implemented since my power supply would die during start up without it). I'm somewhat curious if my inductor got damaged before I got a soft start in there - so I may try dropping in a new inductor as well. Seems unlikely, but who knows. I think I'll slow down the soft start as well (during soft start mode, which lasts 1/4 of a second, I only allow it to increase duty cycle once every other control loop cycle, so at 1024Hz. I'm going to change that to something even less aggressive like 256Hz).

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Hey George, I think you mistook svofski for the thread opener.

But still, thanks for that explanation.

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Since a Vgs swing of 10V at 10ns time is considered to be an excellent gate switch I think that you are more than good.

Have you checked for any excessive ringing at the Drain? That would mean that the inductor and/or the PCB have high parasitic inductance that would need a snubber to dump the transients that could violate any of the FET's parameters; but that FET has a 550V Vds... If, again, you were running the modulator too fast, you could not saturate the inductor; you would just not charge it with enough energy to return back to the load.
Right now, I cannot think of something else.

-George

EDIT: Oops... Mike, I think you are right. And, thank you!
Michael, I am sorry for hijacking the thread... Would you like me to move the irrelevant message?

I hope for nothing; I fear nothing; I am free. (Nikos Kazantzakis)

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It doesn't matter who started this, Giorgos' explanation is still great and highly valued. Thanks, Giorgos! If you would like to continue talking about power conversion, I welcome you in my 1kV thread next to this one. Bait: I have successfully killed an IRF630N with only a 12V 2A power supply! Killing an IRF630N with so little is a great honour, but I'm looking for ways to avoid unnecessary soldershed.

Wouldn't a snubber circuit sort of ruin it for a boost converter?

The Dark Boxes are coming.

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Well, inductor temperature rise comes from only one thing: losses.

There are two significant losses. One is the wire resistance. This gives you heating proportional to the average current. The other is core, generally due to saturation. Saturation always happens at ripple peaks because the nonlinearity is instantaneous, rather than average.

Be careful when you measure current, especially at 250KHz. A good indicator of core behavior is to measure the voltage across the inductor. You need two well-matched probes and a scope that is capable of proper differential operation. One probe at each end of the inductor; subtract the load-side voltage from the source-side voltage. If the core is saturating, you will not see a triangle or exponential type waveform. Instead, the slope will increase at the high-current peaks (the peaks will look "sharper" than they should be).

One of the things you have NOT said is how this behaves with load. Do the inductor and the FET stay hot at light load and get hotter as the load increases? Or, are they always hot, no matter what the load?

I would like to see waveforms for the voltages at all three FET terminals and across the load. Without these, we are pretty much shooting in the dark.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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I favor Giorgos' suggestion of the Miller effect. That sharp, large magnitude drain voltage may be capacitively coupling to the gate and slowing the rise time. Layout may have something to do with it. If the FET doesn't turn off fully and dump all the energy in the inductor, the next charge cycle starts while there is still stored magnetic energy. This is cumulative, and after a number of cycles like this the accumulated magnetic energy will saturate even a large core.

I've taken to using tapped inductors for HV boost circuits. Inductors with two parallel coils are common these days. Connect the coils in series and connect the FET to the center tap. That way the FET drain only sees half the peak output voltage and all the usual problems are reduced proportionally.

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Another thing that is likely happening here is that the saturation current drops as the core heats up. That is, it takes less current to saturate. It is related to the Curie Temperature of the core material. It turns into a positive feedback mechanism.

Core or coil heating warms the core. Saturation current drops. Core starts to saturate at ripple peaks, even if it was not saturating at the start. Additional heating occurs, dropping the saturation current more, resulting in more heating. Etc.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Quote:
I'm looking for ways to avoid unnecessary soldershed.

Svo, I can't help but marvel at your grasp of the English language, to make a subtle joke like that. A lot of native English speakers wouldn't even get it.

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Giorgos_K wrote:
Since a Vgs swing of 10V at 10ns time is considered to be an excellent gate switch I think that you are more than good.

Have you checked for any excessive ringing at the Drain? That would mean that the inductor and/or the PCB have high parasitic inductance that would need a snubber to dump the transients that could violate any of the FET's parameters; but that FET has a 550V Vds... If, again, you were running the modulator too fast, you could not saturate the inductor; you would just not charge it with enough energy to return back to the load.
Right now, I cannot think of something else.

-George

EDIT: Oops... Mike, I think you are right. And, thank you!
Michael, I am sorry for hijacking the thread... Would you like me to move the irrelevant message?


George - ringing is fairly non-existent on the drain. There is a small amount of ringing on the rising edge of the gate, but that is not visible on the drain.

I did, however, realize that my gate driver is only driving my gate down to about 1V. It should still be fully off, but it's not as low as I thought it was. I have an improvement that I will test soon that should bring that down to about 0.7V or so.

No worries about any hijacking! Your post is full of useful information and it'd be a pity to remove it :)

-Michael

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OK I slowed down the PWM to 125KHz and saw some super interesting things. In the photos, the square wave is the FET gate, and the other thing is the FET drain. Notice that it actually has two peaks, and that one of those peaks is affecting the gate voltage.

Any ideas?

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More stuff I'm seeing: my 12V power supply is dipping to about 8V during the part of the output ripple waveform where it is increasing in voltage. Throwing a massive 2.2mF capacitor lessens this (maybe halves it) but it's still there.

I think tomorrow I'm going to try and put some current sensing on the inductor. This is all fairly strange.

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You can use the inductor's own coil resistance as a current sensor. Just measure the resistance of the coil, and as stated above measure the differential voltage between both ends of the inductor. Mr. Ohm will do the rest for you.

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OK I think I understand what is happening here: When my duty cycle is too low, the inductor doesn't have enough energy in it to overcome the capacitance on it, so it just charges the capacitance till its current drops to zero, then that capacitance discharges into the inductor till the voltage hits zero, than the inductor charges the capacitance, etc - it resonates.

In the plot that shows every other pulse being enough to charge the output - the inductor is charging up on the first pulse, and then the timing is right on the second one and it continues getting charged on the second pulse.

So I think I should implement a fixed on time, variable off time controller. Making sure the on time is plenty to charge it.

Opinions?

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Your inductor doesn't charge the capacitor at all unless it exceeds the voltages currently on it. I see that in your lower trace - it just isn't making it. If it did, the peaks would have a flat top. All the energy, therefore, is being dissipated in the FET. The second peak does look like ringing, but I can hardly imagine you have enough stray capacitance on the drain for that sort of time constant. More likely the FET is turning on again, possibly the body diode is avalanching, and the second peak is a second turnoff. If you connected the top of the coil to 12V you would expect to see 0V with the FET on, a high peak when it turns off and then a steady 12V during the rest of the off period. I don't see the steady 12V anywhere.

D'oh - you have the drain trace AC coupled, that's why there's no 12V. I bet a lot of other relevant detail is also lost. I could probably tell you a lot more if I could see it DC coupled.

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peret wrote:
Your inductor doesn't charge the capacitor at all unless it exceeds the voltages currently on it. I see that in your lower trace - it just isn't making it. If it did, the peaks would have a flat top. All the energy, therefore, is being dissipated in the FET. The second peak does look like ringing, but I can hardly imagine you have enough stray capacitance on the drain for that sort of time constant. More likely the FET is turning on again, possibly the body diode is avalanching, and the second peak is a second turnoff. If you connected the top of the coil to 12V you would expect to see 0V with the FET on, a high peak when it turns off and then a steady 12V during the rest of the off period. I don't see the steady 12V anywhere.

D'oh - you have the drain trace AC coupled, that's why there's no 12V. I bet a lot of other relevant detail is also lost. I could probably tell you a lot more if I could see it DC coupled.


Sorry, I should have been more clear: I meant that when the inductor is not charged enough it can't overcome the FET's capacitance and then the FET's capaictance and the inductor resonate. I agree that the FET's body diode is at play here too.

I don't think the drain was AC coupled, but I'll have to check.

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nleahcim wrote:
I don't think the drain was AC coupled, but I'll have to check.

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Quote:
You can use the inductor's own coil resistance as a current sensor. Just measure the resistance of the coil, and as stated above measure the differential voltage between both ends of the inductor. Mr. Ohm will do the rest for you.

Nice joke.
When the inductor current increases, it has across it 12V - Mosfet voltage drop. When the current decrease, it has 220 - 12V. After this, if it is working in discontinuous mode will self oscillate.
Some other people claim to measure the current through Mosfet measuring the drena-source voltage, assuming a known resistance. Just theories, since the drena - source voltage when off is too high to allow a voltmeter or scope to accurately measure it.
Best way is the old way: put a series resistor between "-" and source and measure it, see it on the scope. Sure, with any comfort comes the price: extra loses on the resistor. Do not use a wound resistor.
Any decent power supply has some means for over currents. The boost topology is evil if you "forget" the transistor ON.
Me, I would use one of the hundreds of specialized chips for this purpose.

Quote:
The problem is that the drain of my FET, once Vgs is brought low, often won't make it high enough to charge the output capacitors. Like there is a large delay from when the FET turns off to when the drain swings high, and by that time often the FET is already being turned on again so the drain falls down immediately. During the part of the output triangle wave where the output is dropping slowly, the drain *never* makes it high enough to charge the output capacitor. During the part of the triangle waveform where the output is increasing, the drain makes it high enough to charge the output capacitors about once every other cycle (so about at 125KHz).

It looks the loop regulation is not working well. When you see the drain voltage is not reaching 220V, this means the micro has reduced the PWM duty cycle because is sees enough voltage on the capacitors. Your loop regulation is too simple. Use at least a true proportional regulation and make it faster than the output voltage oscillate. Or even add the derivative component to the loop. It will eat a good chunk of the CPU time. Another way is to increase the output capacitors. Check the ADC accuracy and all your math in the loop regulation also.
I am not sure I understand your scope pictures, for how long time the transistor is ON on the first picture ?
And ah, I should have start with saying that the transistor used is way to big comparing the inductor. Much of the work the inductor has to do is to charge and discharge the transistors capacitance. That transistor is fit for hundreds watts power supply.
George.

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Quote:
The second peak does look like ringing, but I can hardly imagine you have enough stray capacitance on the drain for that sort of time constant. More likely the FET is turning on again, possibly the body diode is avalanching, and the second peak is a second turnoff. If you connected the top of the coil to 12V you would expect to see 0V with the FET on, a high peak when it turns off and then a steady 12V during the rest of the off period. I don't see the steady 12V anywhere.

It is a ringing and not a second mosfet turn on. Since the drain reaches over 100V, on the negative side should ring symmetrically, at - 88V, but this is not possible because the mosfet diode. It can nicely be seen how the wave is distorted by the mosfet and diode capacitance when approaches zero volts. Now since the inductance needs to discharge on only 12V, will take longer to do it and when it does, to reach back 12V potential it has to recharge back those big mosfet and diode capacitance, so it gets charged (the inductor) again so the second pick. If the gate pulse would come much late, we would see more picks, smaller and smaller in amplitude. It is definitely a discontinuous mode operation with badly chosen components.
George.

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angelu wrote:
Quote:
You can use the inductor's own coil resistance as a current sensor. Just measure the resistance of the coil, and as stated above measure the differential voltage between both ends of the inductor. Mr. Ohm will do the rest for you.

Nice joke.
When the inductor current increases, it has across it 12V - Mosfet voltage drop. When the current decrease, it has 220 - 12V. After this, if it is working in discontinuous mode will self oscillate.
Some other people claim to measure the current through Mosfet measuring the drena-source voltage, assuming a known resistance. Just theories, since the drena - source voltage when off is too high to allow a voltmeter or scope to accurately measure it.
Best way is the old way: put a series resistor between "-" and source and measure it, see it on the scope. Sure, with any comfort comes the price: extra loses on the resistor. Do not use a wound resistor.
Any decent power supply has some means for over currents. The boost topology is evil if you "forget" the transistor ON.
Me, I would use one of the hundreds of specialized chips for this purpose.

Quote:
The problem is that the drain of my FET, once Vgs is brought low, often won't make it high enough to charge the output capacitors. Like there is a large delay from when the FET turns off to when the drain swings high, and by that time often the FET is already being turned on again so the drain falls down immediately. During the part of the output triangle wave where the output is dropping slowly, the drain *never* makes it high enough to charge the output capacitor. During the part of the triangle waveform where the output is increasing, the drain makes it high enough to charge the output capacitors about once every other cycle (so about at 125KHz).

It looks the loop regulation is not working well. When you see the drain voltage is not reaching 220V, this means the micro has reduced the PWM duty cycle because is sees enough voltage on the capacitors. Your loop regulation is too simple. Use at least a true proportional regulation and make it faster than the output voltage oscillate. Or even add the derivative component to the loop. It will eat a good chunk of the CPU time. Another way is to increase the output capacitors. Check the ADC accuracy and all your math in the loop regulation also.
I am not sure I understand your scope pictures, for how long time the transistor is ON on the first picture ?
And ah, I should have start with saying that the transistor used is way to big comparing the inductor. Much of the work the inductor has to do is to charge and discharge the transistors capacitance. That transistor is fit for hundreds watts power supply.
George.

George - why do you say the FET is too big? It is rated for about 20x the current I'm operating it at - do you think that is excessive? I'd be happy to try another if you want to suggest one (note that I'm already committed to the DPAK package). I'm thinking the Alpha and Omega AOD4S60 looks decent - it has about a fourth of the Coss.

As for your question regarding the scope picture - the FET is on for about 4us/cycle in the first photo.

I do plan on trying to implement a PID controller on here. Hopefully I can do that soon.

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OK - much playing tonight. My code is now running a fixed on time, variable off time control loop. I had to play with the on time a bit to find something that worked well - but I found 12-16us to work well.

With this new scheme - after the FET turns off, the inductor always is able to discharge into the load. There still is another, smaller peak after that, and occasionally even a third one after that. Looks like it'd keep ringing if I didn't turn on the FET again.

However, I now have about 2V peak to peak noise on my output at maximum load, and my inductor and FET are definitely warm, but not scalding at all. At 1/8th of max load, peak to peak on output is well under a volt.

This is showing a lot of promise. I think perhaps with a lower capacitance FET I can get this even better.

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AOD4S60 looks good.

A 270uH inductance connected to 12V for 14us reaches 0.62A, so a 4A transistor is more than enough.
For only 4us it reaches only 0.17A and it may not be able even to tough 220V.

For light loads you may consider to send pulses in bursts, and to limit the minimum ON time for the transistor.

Look at Viper 12, Viper22, Viper16, Viper17. I would use one of them instead a micro.

And what happens if your load gets damaged it it clamps the output voltage to 50V for example ? I think the micro will pump more current until will get in continuous mode and the converter will get toasted.
You need some protections.
George.

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Quote:

George - why do you say the FET is too big? It is rated for about 20x the current I'm operating it at - do you think that is excessive? I'd be happy to try another if you want to suggest one (note that I'm already committed to the DPAK package). I'm thinking the Alpha and Omega AOD4S60 looks decent - it has about a fourth of the Coss.

As for your question regarding the scope picture - the FET is on for about 4us/cycle in the first photo.

I do plan on trying to implement a PID controller on here. Hopefully I can do that soon.

The problem with big FETs is that while they tend to have lower ON resistance, they have much larger gate charges. This makes turning them on and off fast difficult, and requires larger amounts of current in burst to drive their gate. 20x the current you expect is excessive IMO. I would shoot towards 2x or 3x the expected maximum, while trying to minimize gate charge and RDSon. If you chose it for safety, what's the point of saving one FET if the rest of the board catches on fire anyways...

Because much of the loss in a switching regulator is from the actual switching, minimizing the time the switch spends in between fully off and fully on is key to efficiency. Lower switching frequency also reduces total switching time, improving on efficiency. So a low gate charge MOSFET, with a low DC resistance coil, and low ESR caps with a fast gate driver at a low frequency is what you want.

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OK - so an update:

I switched in the AOD4S60. Circuit seemed to cool down a bit, though I forgot to measure it. Ringing definitely improved significantly.

I also implemented a PID controller. I am sticking with the fixed on time, but the PID regulated the off time. Now my ripple is about 1 bit (~0.25V).

I also played around with the diode a bit. I tried to find some lower output capacitance diodes, though from running the math on them I didn't expect it to make a significant difference. The math didn't lie - the difference between the three diodes was almost not measurable - but actually the original diode that I chose proved to be best.

Both the inductor and the FET sit at about 10 degrees C above ambient when at full load.

I think I'm going to call this solved, at this point.

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So, the problem of the original design seems to be existing at the gate driver stage, since the advertised total gate charge for the ST FET is 27 nC while it is only 6 nC for the ΑΩ part. More specifically, according to the data sheets gate charge charts of the parts, the ST FET needs at least a 20..25 nC gate charge in order to bring Vds down to acceptably low levels, while the ΑΩ FET needs less than 4 nC for that. A steeper gate driver can definitely improve ringing.

Can you post the gate driver stage?

-George

I hope for nothing; I fear nothing; I am free. (Nikos Kazantzakis)

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Giorgos_K wrote:
So, the problem of the original design seems to be existing at the gate driver stage, since the advertised total gate charge for the ST FET is 27 nC while it is only 6 nC for the ΑΩ part. More specifically, according to the data sheets gate charge charts of the parts, the ST FET needs at least a 20..25 nC gate charge in order to bring Vds down to acceptably low levels, while the ΑΩ FET needs less than 4 nC for that. A steeper gate driver can definitely improve ringing.

Can you post the gate driver stage?

-George


I'm pretty confident that the gate driver is OK. With the larger FET, rise/fall times were around 20ns. I haven't checked it with the smaller FET. But that's plenty fast enough IMHO. I mean really, switching to the fixed on time control loop almost completely fixed my problem. The new, smaller FET just improved things a teeny bit.