atmega16 interrupts

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hi men

please can any one help me?

how an interrupt occurs in atmega16?

how an interrupt address determined?

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An "interrupt" is any event that is defined by the designers of the chip to cause a program jump to an interrupt vector. An interrupt can be caused by the reception of a character by the UART or by a logic change on a pin or many other things. But, the function is built into the chip. For example, you cannot create an automatic interrupt if the power supply voltage changes because the designers did not build that in.

There are two "addresses". One is the address of the vector. It is predefined. Each interrupt has its own vector location. If you are writing in c, this is handled automatically for you. If you write in assembler, you have to look up the vector location for each interrupt you want to use. Its in the spec sheet.

There is also the address of the interrupt service routine (ISR). It can be anywhere (in al but the very largest devices, I think). If you use c, you specify the interrupt by name and the compiler puts the proper ISR address into the proper vector location. If you use asm, you need to label the ISR and reference that label in the proper vector location.

There is a chapter in the spec sheet on interrupts. You should review that, carefully. If you use gcc, then you should review the documentation for avrlibc.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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thank you for reply

please can give a simple example in asm. language?

again, thank you very much :D

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Quote:
please can give a simple example in asm. language?

There are examples of how to implement ISR's in the relevant data sheets and in the Tutorial area of the Forum.

Charles Darwin, Lord Kelvin & Murphy are always lurking about!
Lee -.-
Riddle me this...How did the serpent move around before the fall?

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Have you looked at the mega16 datasheet? There is an example of the interrupt vector table in assembly.

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thank you all ka7ehk,LDEVRIES and dksmall

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Show us what you have tried, and then we will help with the details.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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This is an example of some interrupt vectors, placed just below reset vector where program start.

.cseg
	jmp	do_reset		;program start
			
.org	int1addr
	jmp	enter_sleep		;SHUT DOWN and SLEEP

.org	wdtaddr
	jmp	dog_time		;save RTC

.org	ovf2addr
	inc	rtc			;tick RTC
	reti				;return ISR

.org	ovf0addr
	dec	data			;tick TIMER
	reti				;return ISR

do_reset:
	ldi	temp,high(ramend)	;set
	out	sph,temp		;STACK POINTER
	ldi	temp,low(ramend)	;at
	out	spl,temp		;RAMEND

This is an example of how to catch one of the interrupts in an ISR(InterruptServiceRoutine).

enter_sleep:
   some code, as short as possible
   reti      

RETI will enable global interrupts again that was automagically disabled when the interrupt happened and return to the next instruction in main from where main was interrupted.

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Quote:

This is an example of some interrupt vectors, placed just below reset vector where program start.
Code:
.cseg
jmp do_reset ;program start
...
.org ovf2addr
inc rtc ;tick RTC
reti ;return ISR

.org ovf0addr
dec data ;tick TIMER
reti ;return ISR
...


Hmmm--Clever, at first glance. Pack two 1-word instructions into a 2-word vector slot.

However, you WILL burn yourself eventually if you use the above in a real app. INC/DEC modify several processor flags.

You could, however, set a flag in GPIOR0 or other low I/O register with SBI/CBI.

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I must admit that those examples were a bit stupid and could confuse.
But...
In my app register RTC is reset to 0 again in main and will never be larger than 2 in worst case.
Register DATA is only used at one place in main, waiting in a loop for USART RX to timeout if no start bit is detected.

uart_rx:
	ldi	data,100		;set RX TIMEOUT
	ldi	temp,0x01		;enable
	sts	timsk0,temp		;TIMER 0 OVF ISR
rx_start:
	sbis	pind,rx_pin		;wait for 
	rjmp	rx_alive		;start bit
	tst	data			;while not zero
	brne	rx_start		;test RX
	rjmp	rx_timeout		;else RX TIMEOUT	

rx_alive:
	sts	timsk0,zero		;disable TIMER 0 IS

But I confess that those were bad examples.

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Quote:

In my app register RTC is reset to 0 again in main and will never be larger than 2 in worst case.

No, that isn't the point. The timer interrupt could fire at any time. The INC and DEC will modify SREG flags, and the SREG is not preserved. Consider these fragments of mainline code:

004ce8 71e0      	ANDI R30,LOW(0x10)
004ce9 f411      	BRNE PC+3
...
004ced 15e9      	CP   R30,R9
004cee f5e8      	BRSH _0x3D9
...
004d3e 2099      	TST  R9
004d3f f149      	BREQ _0x3E2

Consider what happens if the interrupt fires between any of the pairs of instructions. The flags change in your ISR due to the INC/DEC. Upon RETI the improper branch is taken.
The result is chaos. IMO get rid of those clever inline ISRs.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Gee, you're right (of course).
This is from a real app that's been controlling my heating system for ~4 years.
Guess I've been real lucky, lots of conditional tests in the app and it never crashed or behaved ill (after catching some initial bugs of course).

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starman222 wrote:
thank you for reply

please can give a simple example in asm. language?

again, thank you very much :D

Right here :

http://www.avrbeginners.net/

1) Studio 4.18 build 716 (SP3)
2) WinAvr 20100110
3) PN, all on Doze XP... For Now
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Quote:

Guess I've been real lucky,

Your code is probably fairly robust and one "bad" pass won't blow up the house (or at least it has not to date). Trust me, though, (and don't ask how I know) if there >>is<< a one-cycle window the interrupt will eventually peek in there. Hmmm--if the AVR was sleeping waiting for those interrupts then you are probably OK.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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After some thinking(my head hurts) I think I know why it has worked.
Timer interrupt fires twice a second.
Main wait for RTC register to change and then run a number of subroutines that takes appx 300ms and finally go back to wait for next RTC tick.

dream_on:
	tst	rtc			;wait for 
	breq	dream_on		;RTC interrupt
	sbi	pinc,run		;toggle RUN LED
	call	real_time		;do RTC TICK
	rjmp	main			;return MAIN

Never the less a lousy interrupt example for a newbie.

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hi again

are there atmega16 hardware help me how the interrupt

vector address is placed in PC?

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Not sure I understand your question.
Are you asking where on your computer you can find the interrupt vector table for mega16?

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Lennart wrote:
Not sure I understand your question.
Are you asking where on your computer you can find the interrupt vector table for mega16?

no i ask for an interrupt hardware structure

i need a hardware architecture image for atmega16

thank you for reply my dear

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Quote:

no i ask for an interrupt hardware structure

i need a hardware architecture image for atmega16


Every AVR datasheet - including the mega16 - has a full description. I doubt anyone here can assist you in reading.

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There also be a full table in the .inc file for your Mega16 assembler.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Quote:

Every AVR datasheet - including the mega16 - has a full description.

Well, there is indeed information on what happens to our machine code and program counter and such. But there isn't really any detail/diagram on the box "Interrupt Handler" like we see for e.g. I/O pins.

I was confused by OP's mention of "PC". If it is "Program Counter" then I'd agree that the text in the datasheet tells what happens on a practical level for AVR coders. Now, for a chip designer or comparison of architectures then there may be a desire for more detailed information.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Mr. theusch

thank you

i am just want to see how an interrupt are designed in

AtMega16 or any types because i need to know the

design of int0,1,2 (external) about low level,level

trigger and edge trigger,

i searched in internet and datasheet but did not find it.

other question:

this image is from AtMega16 datasheet

My question: how we can clear INTX by writing logic 1

to it (i think we can clear it by writing logic 0 to it)

please explain that

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No you can't clear the interrupt flag by writing a 0 to it! The datasheet is correct. This feature has been discussed at length before. If you wrote 0s to clear, how would you not clear the flags you don't want to? Writing a logic 1 makes perfect sense as you are specific about the flag you want to clear. In this instance, the reading of the flag register is different to the writing of the flag register - they are not the same register. As discussed at length previously, a number of other micros do the same thing.

Interrupts are usually sampled at the time of the instruction fetch. For level triggered interuppts, the level is sampled. If it is active, then the cpu processes the interrupt. For edge trigger, there is a flipflop to capture the edge. The output of the flipflop is used to determine if the interrupt is active. I neglected the priority resolution and enables for simplicity.

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thank you Mr. Kartman i understood it now thank you

again

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i need answer to the questions about timer

1-when Output Compare Interrupt occur?

2-when Timer Overflow Interrupt occur?

3-when Input Capture Interrupt occur?

i want to understand the benefits of each one

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Quote:

1-when Output Compare Interrupt occur?

What does the datasheet say?

Quote:
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1A Flag, located in TIFR1, is set.

Quote:
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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starman222 wrote:
i need answer to the questions about timer

1-when Output Compare Interrupt occur?

2-when Timer Overflow Interrupt occur?

3-when Input Capture Interrupt occur?

i want to understand the benefits of each one

There are multiple tutorials on using the Timers, check them out in that forum .

1) Studio 4.18 build 716 (SP3)
2) WinAvr 20100110
3) PN, all on Doze XP... For Now
A) Avr Dragon ver. 1
B) Avr MKII ISP, 2009 model
C) MKII JTAGICE ver. 1

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This has all the signs of a school assignment to me.

Charles Darwin, Lord Kelvin & Murphy are always lurking about!
Lee -.-
Riddle me this...How did the serpent move around before the fall?