74*165 / 74*595 and SPI

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Hi, I've been lurking in the forums for a while now, but I couldn't find a clear answer on the matter of

What do the 165 and 595 shift registers have to do with the SPI bus ?

I've seen some mentions of them being 'SPI compatibile' and instructions to connect them to SCK/MISO/MOSI pins on a AVR, but don't understand where does the SPI magic kick in.

All of the examples I've seen (except the ones I've overlooked) are (relatively) simple bit banging methods to use these ICs.

My other questions regarding this are
what benefits are there in using SPI to write to/read from these chips,
what exactly does the hardware do in these cases that would otherwise have to be done in software and
how should one properly use SPI communication with these shift registers?

The main reason behind my confusion is that I'm not very familiar with SPI and I'm getting an impression that its something more complicated then it probably is - thus I fail to see how simple ICs like 165 and 595 could actually be compatibile with such protocol.

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SPI is very simple. Wiggle a clock line, and out a new bit of data on the data line with each clock wiggle. There are variations on how many 'bits per bytes' and when the data gets taken relative to the clock line, but all in all, it's just that.

So the SPI hardware does that for you, faster than what you would do with the bitbang, and leaving the AVR cycles available to do other stuff in the meantime.

It's like having a motorized car vs a bicycle.. You CAN get there with the bicycle, but in the car, you'll have spare cycles (sic) to scratch your nose :D

Author of simavr - Follow me on twitter : @buserror

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The spi is just a shift register, and the 165 and 595 are just shift registers. If you have 40 buttons to read, just hang a chain of five 165s out there on the spi, and you've got an input expander. Need to turn on 40 lights? Get 5 of those TI 595s that will hump out 500ma each output and you have a light show.

Imagecraft compiler user

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buserror wrote:
It's like having a motorized car vs a bicycle.. You CAN get there with the bicycle, but in the car, you'll have spare cycles (sic) to scratch your nose :D

More like "Auto-Pilot, " I'd say! Set it and forget it, until the next data byte needs to be sent or received.

Once the SPI system is initialized (the part that seems to confuse everyone) it's a no-brain-er method to move data from one place to another. The dilemma is what the receiving device expects. The 165/595 are about the simplest forms to connect to SPI.

But then too, things like serial EEPROM is really the same simple SPI - it's the correct sequence of data that gets tough but, that really isn't a difficulty with SPI per SE', it's the protocol of the connected device.

You can avoid reality, for a while.  But you can't avoid the consequences of reality! - C.W. Livingston

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SPI in general: http://en.wikipedia.org/wiki/Ser...

It is simple. It is a synchronous serial interface - clocking is provided separately. One wire to send out serial data (MOSI), one wire to receive serial data (MISO), one to clock the sending (SCK), and one wire to address each slave (SS).

Now, the 595 has the following inputs of interest:

Shift clock SCK. This clocks the data into the 595. It happens to fit to the AVRs SCK. So the AVRs SPI interface clocks the data into the 595.

Serial data SER. This is where the bits to clock into the 595 should go. It happens to fit to the AVRs MOSI. So the AVR's SPI master output provides the input for the 595.

Latch clock RCK. This loads the latches of the 595 with the data currently in the 595. In other words, it lets the data appear at the eight output pins. It fits nicely to the AVRs SS output, but this is slightly trick. The 595 transfers the contents of the shift registers to the output latches when RCK transitions from low to high. SS selects a slave by going from high to low, so nothing happens when the slave (the 595) is selected and output starts. But when output is done, and SS deselects the slave, it goes from low to high. And this is exactly the signal needed to let the 595 move the just received data to the latches. That moment you get your serial data back as parallel data.

The 165 has no latches and you can't connect SS. There you can observe how the bits are sequentially shifted through the shift register on the output. So the output signals change their state multiple times before the complete byte is in. This might or might not create problems with the receiver of the eight parallel bits. However, the receiver can still listen to SS and just use the data when SS goes from low to high.

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Thanks for the feedback!

That helped get my mind on the right track, the application note about SPI made more sense now.

However I won't pretend that I'm not lazy, I'd love to see some code samples on how to get this to work with either of these chips.

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These chips work like any other SPI slave.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Quote:
The 165 has no latches and you can't connect SS. There you can observe how the bits are sequentially shifted through the shift register on the output.

Nearly. The 165 is the opposite of a 595 - parallel in, serial out. While /PL is low (parallel load) whatever is presented on A-H is latched into the shift register. When /PL is high, pulses on CP (from SCK) clock the data out of Q7 (to MISO). Cascade by taking Q7 of one 165 to DS of the next.

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peret wrote:

Nearly. The 165 is the opposite of a 595 - parallel in, serial out.

Oh yes. I mixed that up with the 164. I thought the OP was just talking about the two serial to parallel shift registers. The 595 with, the 164 without latches.

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edit: sorry, responded to the wrong thread (two windows open)

mods, please delete.

Last Edited: Sat. Oct 29, 2011 - 11:08 PM
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A 20MHz AVR can clock the SPI at 10MHZ (100ns per tic), so you can shift out a byte in 800ns (1.25megabytes per sec)

Imagecraft compiler user

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Quote:
those TI 595s that will hump out 500ma each output

500ma @ ?.....