For the first time I used the USI as half duplex UART
(see also application note AVR307). Well, it works just
fine. But I think some simple improvements would make the USI even more universal.
1. New feature: Inverse operation direction of the USI
When SPI mode enabled, the MSB is directly connected to
the DO pin and the bits are left shifted out of the
data register. So the MSB is transmitted first. When
receiving data the first incoming bit will end as the
MSB in the buffer register and the last incoming bit
will be located in the LSB of the buffer register.
But for UART transmission the LSB must be send first.
So the bitorder must be reversed whenever sending or
With the new feature enabled the DO pin would be connected
to the LSB in the data register, incoming bits are
stored to the MSB of the data register and the shift
direction is right. So no bit reversing is needed.
I guess this improvement is simple and would cost
only a few silicon.
2. New feature: Enlarge the USI from 8 bits to 12 bits
A standard UART frame takes 10 bits (1 Start, 8 data, 1 stop)
The USI can only handle max. 8 bits. So the data
register must be rewritten during sending an UART
frame. This is very time critical. For exampel: With
a clock of F_CPU = 1 MHz and a UART baudrate of 9600
baud, there are only 104 clock cycles left to update
the data register.
With a 12 bit USI it would be even possible to
implement the USART multi master communication mode
with a low CPU load.
What do you think about my suggestions?
Do you think they're usefull and an enrichment for
the ATtiny family?
Truly, if some of you professional industry developers
aggree to my suggestion, big brother Atmel won't
ignore us. Maybe you have even more reliable ideas.