Sampling rate in ADC in ATMEGA16 ?

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Hello , I am a bit confused about how to calculate the sampling rate in the ADC :

In this tutorial :
https://www.avrfreaks.net/index.p...

The sampling rate was just the : Systemclk/prescalar

But on this topic :
https://www.avrfreaks.net/index.p...

Mike B calculated the sampling rate as Systemclk/noOfCyclesTakenForConversion

which equals SystemClk/13 in free running mode

So where is the right information?

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Quote:
The sampling rate was just the : Systemclk/prescalar
No, this is the ADC clock rate.
Quote:
Mike B calculated the sampling rate as Systemclk/noOfCyclesTakenForConversion
Again incorrect. The sample rate is SystemClk / (pre-scaler * noOfCyclesPerSample). For all but the first sample, noOfCyclesPerSample is 13.

Regards,
Steve A.

The Board helps those that help themselves.

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iA7med wrote:
The sampling rate was just the : Systemclk/prescalar

That's incorrect. The above is the ADC clock frequency ... not sample rate.
A normal conversion takes 13 ADC clock cycles.
ADC sample rate can be what ever you like up to the maximum of 1/conversion time.

Example:
System Clock = 16Mhz
ADC Prescaler = 128
ADC Clk Freq = 125Khz
ADC conversion time = 104us (13 x ADC clk cycles)
Maximum sample rate = 1/104us = 9615 samples/second apprx.

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Quote:

System Clock = 16Mhz
ADC Prescaler = 128
ADC Clk Freq = 125Khz

Also note that sometimes it pays to reduce F_CPU to get as close to the permissible 200kHz as possible.

System Clock = 12.8MHz
ADC Prescaler = 64
ADC Clk Freq = 200Khz
ADC conversion time = 65us (13 x ADC clk cycles)
Maximum sample rate = 1/65us = 15385 samples/second apprx.

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Quote:
ADC conversion time = 104us (13 x ADC clk cycles)
...
ADC conversion time = 65us (13 x ADC clk cycles)

Seems like in the first case ADC clk cycles = 8 whereas its 5 in the 2nd. How do we decide upon that?

AVR Guide and Tutorials
http://maxembedded.wordpress.com

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Quote:

Seems like in the first case ADC clk cycles = 8 whereas its 5 in the 2nd. How do we decide upon that?

1/200kHz = 5us, 1/125kHz = 8us

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maxmiaggi wrote:
Seems like in the first case ADC clk cycles = 8 whereas its 5 in the 2nd. How do we decide upon that?

You simply decide by choosing the sample rate that you require. If you want the highest possible sample rate that will still give accurate 10bit result, then you have to choose the correct system clock in combination with appropriate prescaler division, as per clawson's example.

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@clawson and JimK
thanks.. :)

AVR Guide and Tutorials
http://maxembedded.wordpress.com

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Thank you :)