## My New Year gift to all Freaks - new AVR MEXT opcodes!

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Examining the SP1 .inc files I found a fantastic device - ATMega64HVE - which appears to have an on-chip integer 32/64 math extension engine - MEXT. Further investigations allowed me to reveal the entire new instruction subset and successfully assemble the test code with AVRASM2.

The listing reported total 159 instructions and listed them all (see the code below).

Besides, I discovered four new XMega instructions for enhanced XMega core. Here is the code and listing illustrating all I said above:

```; File MEXT.asm:

#pragma AVRPART CORE EXTENSIONS MEXT 1
; Mega64HVE Math EXTension module instructions:

mul.ll  r0,r8,r16,r24   ; Multiply 64u x 64u = 128u

mulsu.l r0,r4,r8,r12    ; Multiply 32s x 32u = 64s
muls.l  r0,r4,r8,r12    ; Multiply 32s x 32s = 64s
mulu.l  r0,r4,r8,r12    ; Multiply 32u x 32u = 64u
mul.l   r0,r4,r8        ; Multiply 32u x 32u = 32u

mulsu.w r0,r2,r4        ; Multiply 16s x 16u = 32s
muls.w  r0,r2,r4        ; Multiply 16s x 16s = 32s
mulu.w  r0,r2,r4        ; Multiply 16u x 16u = 32u
mul.w   r0,r2,r4        ; Multiply 16u x 16u = 16u

absxt.ll r8             ; Absolute value of 64 bit long long w/sign extend
absxt.l r4              ; Absolute value of 32 bit long w/sign extend

abs.ll  r8              ; Absolute value of 64 bit long long
abs.l   r4              ; Absolute value of 32 bit long

negts.ll r8             ; Negate and toggle sign of 64 bit long long
negts.l r4              ; Negate and toggle sign of 32 bit long

neg.ll  r8              ; Negate a 64 bit long long
neg.l   r4              ; Negate a 32 bit long

ror.ll  r8              ; Rotate right a 64 bit long long
ror.l   r4              ; Rotate right a 32 bit long

asr.ll  r8              ; Arithmetically shift right a 64 bit long long
asr.l   r4              ; Arithmetically shift right a 32 bit long

lsr.ll  r8              ; Logically shift right a 64 bit long long
lsr.l   r4              ; Logically shift right a 32 bit long

tst.ll  r8              ; Test for zero or minus a 64 bit long long
tst.l   r4              ; Test for zero or minus a 32 bit long

mov.ll  r0,r8           ; Move a 64 bit long long
mov.l   r0,r4           ; Move a 32 bit long

div.ll  r0,r8           ; Divide 64u / 64u = 64u.64u
div.l   r0,r4           ; Divide 32u / 32u = 32u.32u

divinit.l r4            ; Initialize a quad register for long division

rsbc.l  r0,r4           ; 32 bit reverse subtract w/carry
rsub.l  r0,r4           ; 32 bit reverse subtract

sbc.l   r0,r4           ; 32 bit subtract w/carry
sub.l   r0,r4           ; 32 bit subtract

cpc.l   r0,r4           ; 32 bit compare w/carry
cp.l    r0,r4           ; 32 bit compare

adc.l   r0,r4           ; 32 bit add w/carry
add.l   r0,r4           ; 32 bit add

;       .lds.l  r4,127          ; Load a 32 bit variable to quad register - didn't work yet listed
;       .sts.l  127,r4          ; Store a quad register to 32 bit variable - didn't work yet listed

#pragma AVRPART CORE CORE_VERSION V3XJ
; New XMega (core V3XJ) instructions:

xch     z,r1            ; Exchange r1 with RAM[Z}

lac     z,r2            ; Load And Clear R2 bits of RAM{Z}
las     z,r3            ; Load And Set R3 bits of RAM{Z}
lat     z,r4            ; Load And Toggle R4 bits of RAM{Z}
.exit

MEXT.lst:

AVRASM ver. 2.1.42  C:\XAVR\Jim\Mega64HVE.asm Thu Dec 31 12:02:16 2009

; Mega64HVE Math EXTension module instructions:

000000 fd1c 0880        mul.ll  r0,r8,r16,r24   ; Multiply 64u x 64u = 128u

000002 fc8e 0740        mulsu.l r0,r4,r8,r12    ; Multiply 32s x 32u = 64s
000004 fc8e 0640        muls.l  r0,r4,r8,r12    ; Multiply 32s x 32s = 64s
000006 fc8e 0540        mulu.l  r0,r4,r8,r12    ; Multiply 32u x 32u = 64u
000008 fc4c 0040        mul.l   r0,r4,r8        ; Multiply 32u x 32u = 32u

00000a fc2a 0300        mulsu.w r0,r2,r4        ; Multiply 16s x 16u = 32s
00000c fc2a 0200        muls.w  r0,r2,r4        ; Multiply 16s x 16s = 32s
00000e fc2a 0100        mulu.w  r0,r2,r4        ; Multiply 16u x 16u = 32u
000010 fc2a 0000        mul.w   r0,r2,r4        ; Multiply 16u x 16u = 16u

000012 92b7             absxt.ll r8             ; Absolute value of 64 bit long long w/sign extend
000013 9257             absxt.l r4              ; Absolute value of 32 bit long w/sign extend

000014 92b6             abs.ll  r8              ; Absolute value of 64 bit long long
000015 9256             abs.l   r4              ; Absolute value of 32 bit long

000016 92b5             negts.ll r8             ; Negate and toggle sign of 64 bit long long
000017 9255             negts.l r4              ; Negate and toggle sign of 32 bit long

000018 92b4             neg.ll  r8              ; Negate a 64 bit long long
000019 9254             neg.l   r4              ; Negate a 32 bit long

00001a 92a7             ror.ll  r8              ; Rotate right a 64 bit long long
00001b 9247             ror.l   r4              ; Rotate right a 32 bit long

00001c 92a6             asr.ll  r8              ; Arithmetically shift right a 64 bit long long
00001d 9246             asr.l   r4              ; Arithmetically shift right a 32 bit long

00001e 92a5             lsr.ll  r8              ; Logically shift right a 64 bit long long
00001f 9245             lsr.l   r4              ; Logically shift right a 32 bit long

000020 92a4             tst.ll  r8              ; Test for zero or minus a 64 bit long long
000021 9244             tst.l   r4              ; Test for zero or minus a 32 bit long

000022 fe2d             mov.ll  r0,r8           ; Move a 64 bit long long
000023 fe0b             mov.l   r0,r4           ; Move a 32 bit long

000024 fe2c             div.ll  r0,r8           ; Divide 64u / 64u = 64u.64u
000025 fe0a             div.l   r0,r4           ; Divide 32u / 32u = 32u.32u

000026 fe6b             divinit.l r4            ; Initialize a quad register for long division

000027 fa2b             rsbc.l  r0,r4           ; 32 bit reverse subtract w/carry
000028 fa0b             rsub.l  r0,r4           ; 32 bit reverse subtract

000029 f82b             sbc.l   r0,r4           ; 32 bit subtract w/carry
00002a f80b             sub.l   r0,r4           ; 32 bit subtract

00002b fa2a             cpc.l   r0,r4           ; 32 bit compare w/carry
00002c fa0a             cp.l    r0,r4           ; 32 bit compare

00002d f82a             adc.l   r0,r4           ; 32 bit add w/carry
00002e f80a             add.l   r0,r4           ; 32 bit add

;      .lds.l  r4,127          ; Load a 32 bit variable to quad register - didn't work yet listed
;      .sts.l  127,r4          ; Store a quad register to 32 bit variable - didn't work yet listed

#pragma AVRPART CORE CORE_VERSION V3XJ
; New XMega (core V3XJ) instructions:

00002f 9214             xch     z,r1            ; Exchange r1 with RAM[Z}

000030 9226             lac     z,r2            ; Load And Clear R2 bits of RAM{Z}
000031 9235             las     z,r3            ; Load And Set R3 bits of RAM{Z}
000032 9247             lat     z,r4            ; Load And Toggle R4 bits of RAM{Z}

RESOURCE USE INFORMATION
------------------------

Notice:
The register and instruction counts are symbol table hit counts,
and hence implicitly used resources are not counted, eg, the
'lpm' instruction without operands implicitly uses r0 and z,
none of which are counted.

x,y,z are separate entities in the symbol table and are
counted separately from r26..r31 here.

.dseg memory usage only counts static data declared with .byte

Register use summary:
r0 :  21 r1 :   1 r2 :   5 r3 :   1 r4 :  28 r5 :   0 r6 :   0 r7 :   0
r8 :  15 r9 :   0 r10:   0 r11:   0 r12:   3 r13:   0 r14:   0 r15:   0
r16:   1 r17:   0 r18:   0 r19:   0 r20:   0 r21:   0 r22:   0 r23:   0
r24:   1 r25:   0 r26:   0 r27:   0 r28:   0 r29:   0 r30:   0 r31:   0
x  :   0 y  :   0 z  :   4
Registers used: 10 out of 35 (28.6%)

Instruction use summary:
.lds  :   0 .sts  :   0 abs.l :   1 abs.ll:   1 absxt.l:   1 absxt.ll:   1
adc   :   0 adc.l :   1 add   :   0 add.l :   1 adiw  :   0 and   :   0
andi  :   0 asr   :   0 asr.l :   1 asr.ll:   1 bclr  :   0 bld   :   0
brbc  :   0 brbs  :   0 brcc  :   0 brcs  :   0 break :   0 breq  :   0
brge  :   0 brhc  :   0 brhs  :   0 brid  :   0 brie  :   0 brlo  :   0
brlt  :   0 brmi  :   0 brne  :   0 brpl  :   0 brsh  :   0 brtc  :   0
brts  :   0 brvc  :   0 brvs  :   0 bset  :   0 bst   :   0 call  :   0
cbi   :   0 cbr   :   0 clc   :   0 clh   :   0 cli   :   0 cln   :   0
clr   :   0 cls   :   0 clt   :   0 clv   :   0 clz   :   0 com   :   0
cp    :   0 cp.l  :   1 cpc   :   0 cpc.l :   1 cpi   :   0 cpse  :   0
dec   :   0 des   :   0 div.l :   1 div.ll:   1 divinit.l:   1 eicall:   0
eijmp :   0 elpm  :   0 eor   :   0 fmul  :   0 fmuls :   0 fmulsu:   0
icall :   0 ijmp  :   0 in    :   0 inc   :   0 jmp   :   0 lac   :   1
las   :   1 lat   :   1 ld    :   0 ldd   :   0 ldi   :   0 lds   :   0
lpm   :   0 lsl   :   0 lsr   :   0 lsr.l :   1 lsr.ll:   1 mov   :   0
mov.l :   1 mov.ll:   1 movw  :   0 mul   :   0 mul.l :   1 mul.ll:   1
mul.w :   1 muls  :   0 muls.l:   1 muls.w:   1 mulsu :   0 mulsu.l:   1
mulsu.w:   1 mulu.l:   1 mulu.w:   1 neg   :   0 neg.l :   1 neg.ll:   1
negts.l:   1 negts.ll:   1 nop   :   0 or    :   0 ori   :   0 out   :   0
pop   :   0 push  :   0 rcall :   0 ret   :   0 reti  :   0 rjmp  :   0
rol   :   0 ror   :   0 ror.l :   1 ror.ll:   1 rsbc.l:   1 rsub.l:   1
sbc   :   0 sbc.l :   1 sbci  :   0 sbi   :   0 sbic  :   0 sbis  :   0
sbiw  :   0 sbr   :   0 sbrc  :   0 sbrs  :   0 sec   :   0 seh   :   0
sei   :   0 sen   :   0 ser   :   0 ses   :   0 set   :   0 sev   :   0
sez   :   0 sleep :   0 spm   :   0 st    :   0 std   :   0 sts   :   0
sub   :   0 sub.l :   1 subi  :   0 swap  :   0 tst   :   0 tst.l :   1
tst.ll:   1 wdr   :   0 xch   :   1
Instructions used: 42 out of 159 (26.4%)

Memory use summary [bytes]:
Segment   Begin    End      Code   Data   Used    Size   Use%
---------------------------------------------------------------
[.cseg] 0x000000 0x000066    102      0    102 unknown      -
[.dseg] 0x000060 0x000060      0      0      0 unknown      -
[.eseg] 0x000000 0x000000      0      0      0 unknown      -

Assembly complete, 0 errors, 0 warnings

```

Enjoy, and Happy New Year to all! :P

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

Total votes: 0

What? No mac instruction?

Total votes: 0

Quote:

What? No mac instruction?

I was surprised that the Xmega didn't add that.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Total votes: 0

Great,those 32bit and 64 bit instructions are really usefull.
Well done MBedder.

Total votes: 0

:) :)

Nobody can go back and start a new beginning, but anyone can start today and make a new ending.

Last Edited: Fri. Jan 1, 2010 - 10:37 AM
Total votes: 0

Quote:
the price of ATmega64
I don't think this is a standard M64. And when will the chip be available and who will be able to buy it?

The only reference to the chip on the Atmel site is...this thread. :shock:

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

Total votes: 0

:) :)

Nobody can go back and start a new beginning, but anyone can start today and make a new ending.

Last Edited: Fri. Jan 1, 2010 - 10:38 AM
Total votes: 0

How do we know that this is not a hoax or a "New Years Fool" story?

Jim

Until Black Lives Matter, we do not have "All Lives Matter"!

Total votes: 0

ka7ehk wrote:
How do we know that this is not a hoax or a "New Years Fool" story?

Jim

I created a project to test it out and it assembles for me.

~~John

Total votes: 0

:)

Nobody can go back and start a new beginning, but anyone can start today and make a new ending.

Total votes: 0

AVR Studio 5: Release 5.0 beta 2 release notes lists the mega64hve as obsolete. The original release notes for AS4.18 release 3 10/2009 shows it being supported since 4.17. These are the only hits in a search of Atmels website. Did this processor ever exist as real silicon?

Total votes: 0

It may have been a customized variant for a high volume customer, or a proposed device that never made it past the engineering stage.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

Total votes: 0

A perfect example of paperware :D

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.