I have the impression that during a debug session (GCC debugger active and MK-II connected to PDI) TWI clock is reduced.
Using a logic state analyser I see that during normal operation the clock is 100 kHz, while during debug speed lowers to 3,12 kHz (that is 1/32 of normal speed).
I suppose this is normally not a problem, after all slaves adapt their speed to master clock. In my case this is a problem because I have to synchronise certain actions with SCL.
Apart from this: did you experience the same problem?
Before contacting Atmel support I would share your opinion.