I'm in the process of designing a data capture and feedback loop control system. The system is comprised of five AD7685 ADCs (http://www.analog.com/static/imp...) that will be read at a sampling rate of no more than 1 kHz.
A sample is initiated by bringing high a CNV pin on the ADCs. All CNV pins of the ADCs are wired together. Each of the five ADCs are then read over SPI in sequential order.
I then have to compare the voltage sampled from one ADC with a known value. If the sampled voltage is greater than this known value, I need to send a control word to an SPI DAC (AD5621, http://www.analog.com/static/imp...).
I've selected the ATMEGA324P-20AU as the microcontroller used to implement this system.
Once I've collected data from each of the five ADCs, I need to send the data over a serial port to a 32-bit ARM microcontroller running Linux. I assume that serial port communications will occur at 115200 baud.
(1) What should I choose as the clocking frequency of the ATMEGA?
(2) Is it possible to sustain a sampling rate of 1 kHz from the 5 ADCs over the serial port?
(3) Suppose that I compute a CRC checksum. What should be the length of the checksum, and would I still be able to sustain this sampling rate while calculating the checksum?
Could anyone comment on this scheme?