AVR Freaks

Lee, I don't think a proper macro for twiddling JTD exists yet in avr-libc.

However, a macro such as this ought to work, and be guaranteed regardless of optimization level, and safe from interruption:

Pass the macro either true or false, depending on whether you want to disable the jtag (true) or enable it (false).

But this has evolved into a discussion of inline assembly and most definitely qualifies as a GCC-specific discussion. So if a mod wouldn't mind moving it into the avr-gcc forum, I think all the non-GCC users would thank you.

So that I spend the absolute minimum possible amount of time in an interrupt-inhibited state.

There was a lengthy discussion about this in the past with regards to GCC automatically inhibiting and re-enabling interrupts surrounding its direct manipulations of the stack pointer during function entry and exit to allocate space for local variables. Basically, following any 0->1 transition of the I bit in SREG (regardless of the cause) the AVR always runs at least 1 more instruction from the current line of execution before any interruption is possible.

I know this is an ancient thread, but the solution is useful to others searching for current problems.

I have used @attigeeks solution of :-

MCUCSR=0x80;
MCUCSR=0x80;

and it works fine (previous attempt of MCUCSR|=_BV(JTD) did not.

If the avr-gcc Compiler was a little more clever it could possibly manage a read-modify-write in a single instruction. e.g. SBI
The straightforward assignments are often managed 'better' by most compilers. All the same, the '0x80' needs to be put into a register befor you can use OUT.
kscharf's solution will probably work even with avr-gcc in brain-dead mode (-O0)

Note that the 'register' modifier does not guarantee anything in C.

So actually this particular operation is an ideal candidate for a 'avr-libc.a' function.

The alternative is for avr-gcc to alter the brain-dead interpretation of -O0. i.e. allow 100% safe and reliable peephole optimisations, yet not re-arrange code. I will not hold my breath !!

David.

Yeah that IS brain dead. It is loading Z THREE TIMES to access the MCUCR when ONE will do. Heck, what I would do is to write my own assembly language function that returns nothing and takes nothing. It would only have to have 7 instructions and would use the 'temp' register. Would be callable from "C".

IE:
NOJTAG.S
global NoJtag
NoJtag:
LDI R30,0x55
LDI R31,0x00
LDD R24,Z+0
ORI R0,0x80
STD Z+0,R0
STD Z+0,R0
RET

Actually to be truly C compatible it might have to first save the 'Z' register and restore it on the way out.

I built it with gcc 01 optimisation and it definately works in C using MCUCSR=0x80. In my instance I don't care about the other bits.

I am suprised their isn't better Atmel / compiler support for this, because without using some method like this you can't get the micro to sleep properly. Before getting this working the best power save mode sleep current I could get was 150uA, now the JTAG is disabled (in sleep only) I get 20uA. I switch the bits zero again on wake-up.
In my instance I use a AVR JTAG MKII, so if I switch off the fuses, I get an un-programmable device.

Writing to this register in C without checout ORing the contents is dicey (OK in my instance) and deep diving into assebler isn't for everybody, espcially for a 'standard' feature of sleep.

By the way, thanks everybody for the mass of responses.

Oops. My mistake. Cliff's example was assigning an immediate value not an 'OR' in.

Seeing as how any normal human being can understand:

or

it is clear that avr-gcc performs brain-death intentionally.

As far as I know, IAR, CV, ImageCraft can not be persuaded to generate the extent of brain death achieved by avr-gcc with any optimisation setting. But hey-ho, avr-gcc is cheap.

David.