The AVR datasheets say, that after RETI and SEI, there is always at least one instruction executed until a (potentially pending) interrupt is being serviced.
However, to be able to calculate interrupt latencies exactly - and to be able to write optimal code - we need to know more. The following questions are outstanding:
- does the above apply to situations where the I flag in SREG is changed through changing whole SREG (i.e. through OUT, STS, ST, etc.)? There is ample code out there working out of this assumption (e.g. avr-gcc functions prologue/epologue), and hints here and here, but I cannot find any Atmel-originated information stating clearly that this is the case, i.e. this may unexpectedly change in the future.
- Does the above apply only to the global interrupt flag I? In other words, what happens if a single interrupt is enabled through setting its respective enable flag? If this interrupt is pending at the moment of enabling, will its routine called immediately, or will there be at least one instruction executed after the enabling instruction?
Or, if there is no such, could please the Atmel insiders reading these lines get the Atmel Norway crew to publish a binding explanation, maybe in a form of a short appnote? (I know I could post a question through the support website, but I find this to be a bit more important to all AVR developers than an answer to be communicated to me personally.)