CLR vs LDI

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I wanted to double check difference between CLR and LDI.

Booth will take same space in flash, both will be executed in 1 clock, but the CLR will clear S,V,N and set Z flag. But beside that they will act as very same instruction, I'm right?

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CLR is actually an eor R,R instruction which sets flags as described in the AVR Instruction Set document and works with any register (R0..R31). LDI is just LDI which doesn't alter any flags and works only with upper 16 registers (R16..R31). RTFM.

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

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Don't forget SUB Rn, Rn :twisted:

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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CLR and EOR have the same opcode, SUB has a different one.

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

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Quote:

SUB has a different one.

which is also different from LDI.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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...as well as from the rest of opcodes. What else? :D

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.

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the previous "navel inspection" on this very subject

(thus proving Lee's old adage that there's no subject here that hasn't been discussed before)

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theusch wrote:
Don't forget SUB Rn, Rn :twisted:

And the SUB will clear C and H flags. So for example if I want to clear carry and then clear register I could do it with SUB. That could come handy one day. thanks :)

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clawson wrote:
the previous "navel inspection" on this very subject

(thus proving Lee's old adage that there's no subject here that hasn't been discussed before)

Excellent, thank you. 34 alternatives, that is great :D

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Quote:

34 alternatives, that is great

You haven't actually read it have you? I think the author was surprised that there seemed to many ways and guessed it could be as many as 34. In reality I'm not sure if that thread really lists any more than already exposed here. Like all things in programming - there are always a number of ways to skin a cat!

(hey, just thought but has anyone here or in that thread said "multiply by 0" yet? ;-) If it's a new one do I win something?)

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Quote:
You haven't actually read it have you? I think the author was surprised that there seemed to many ways and guessed it could be as many as 34. In reality I'm not sure if that thread really lists any more than already exposed here. Like all things in programming - there are always a number of ways to skin a cat!

No at that moment no, and I know that no all of them will be always usable and it will be like parkour from A to B instead walking A to B, but still it's nice.

I almost forgot for incrementing 0xff, in one project I have 2 spare registers for 0x00 and 0xff. If I want to save registers I could use 1 and inc and dec it.

And I think MUL is there already, but now I see point of you guys. :D fooling around :)

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Hope the "34 alternatives" was helpful. And "mul x,0" is already listed #25.

Quote:
there are always a number of ways to skin a cat!

But there are "only" 34 ways to make it quick (with AVR).

No RSTDISBL, no fun!

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Keep in mind that the vast majority of those "34 ways" have absolutely no advantage at all over the ways covered in this thread.

Regards,
Steve A.

The Board helps those that help themselves.

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If one does not care about the status register,
then all the ones that work are equivalent.
Otherwise, if Rx>=16,
LDI Rx, 0
will usually do what you want.
If Rx< 16 and you are using avr-gcc,
MOV Rx,R1
will usually do what you want.
Otherwise, get out the data sheet and find the opcode that won't alter your favorite flag.

IN Rx, fred
will work for Rx< 16 if one can find a fred known to be zero.
Reserved bits of unreserved bytes read as 0.
I'm not sure about reserved bytes.

With avr-gcc,
MUL R1, R0
would usually clear R0, but it takes two cycles.

Iluvatar is the better part of Valar.

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Quote:
With avr-gcc,
MUL R1, R0
would usually clear R0, but it takes two cycles.
But if you know that R1 contains zero, how would this be different than MOV R0,R1?

Regards,
Steve A.

The Board helps those that help themselves.

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Koshchi wrote:
Quote:
With avr-gcc,
MUL R1, R0
would usually clear R0, but it takes two cycles.
But if you know that R1 contains zero, how would this be different than MOV R0,R1?
To take the question literally: status registers.
To provide the information I suspect was desired:
I only mentioned MUL because another poster mentioned it,
apparently unaware it was ineligible.
The contest is open to 1-cycle instructions only.
Not my rule.

Iluvatar is the better part of Valar.

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Quote:
The contest is open to 1-cycle instructions only.

You are wrong. Read the opening post:

Quote:
one asm op-code command

This is not the same.
And this is not a contest.

No RSTDISBL, no fun!

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Quote:
And this is not a contest.
No, it is just mental masturbation.

Regards,
Steve A.

The Board helps those that help themselves.

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Quote:

No, it is just mental masturbation

This has got to go down as one of the funniest posts I've ever read here!

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This whole thread is bizarre, but what else is new!

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Ways to clear a register: Number 35:

odokemono. I try to entice electrons to do my bidding.

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That's a nice hammer.
I used that brand relentless in daily work for more than fifteen years before it broke.
Should CLR the most problems...

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odokemono wrote:
Ways to clear a register: Number 35:

There's a name for that technique. It's called "Widlarizing". Read enough Pease and you might come across it. It's a very satisfying technique.