I am using an Atmega328 in SPI mode and is configured as the master. I am transmitting 0XAA in a loop. Looking at the MOSI and the SCK pins, I see the attached waveform. I am seeing a gap after each transmission of 8 bits. The SPI clock polarity is set to falling edge. I assume it is because of the clock staying high for a short time before toggling on the next 8 bit cycle. Why could this be happening?