I would like to go through and figure out what the time duration is of the different interrupts I am using. My main purpose is to try to figure out what the slowest possible response I can expect from the time I recieve a byte on the UART to the the time the RXC interrupt fires.

I will probably be measuring this, making changes, and repeating, so I want to use a quick method that may not be perfectly accurate.

My plan is to go to set an unused pin high in the beginning of the interrupt, then set it low at the end of the interrupt and measure this with my DSO. Of course this does not include the prologue, epilogue, and vector jumps.

Here is an example:

ISR(TIMER1_OVF_vect){ //This is used for long delays in main L1_ON slow_counter.word++; if(inverse_velocity_overflow < 12000){ inverse_velocity_overflow += 1500; if((inverse_velocity_overflow >= 3000) && ((inverse_velocity_overflow - 1500) > encoder.inverse_vel)) encoder.inverse_vel = inverse_velocity_overflow - 1500; } else encoder.inverse_vel = inverse_velocity_overflow; L1_OFF }

My oscilliscope measures this at 4.92 us.

Now I compensate.

ISR(TIMER1_OVF_vect){ 21a: 1f 92 push r1 21c: 0f 92 push r0 21e: 0f b6 in r0, 0x3f ; 63 220: 0f 92 push r0 222: 11 24 eor r1, r1 224: 2f 93 push r18 226: 3f 93 push r19 228: 8f 93 push r24 22a: 9f 93 push r25 //This is used for long delays in main L1_ON 22c: 2b 9a sbi 0x05, 3 ; 5 slow_counter.word++; 22e: 80 91 d1 02 lds r24, 0x02D1 232: 90 91 d2 02 lds r25, 0x02D2 236: 01 96 adiw r24, 0x01 ; 1 238: 90 93 d2 02 sts 0x02D2, r25 23c: 80 93 d1 02 sts 0x02D1, r24 if(inverse_velocity_overflow < 12000){ 240: 80 91 d3 02 lds r24, 0x02D3 244: 90 91 d4 02 lds r25, 0x02D4 248: 80 5e subi r24, 0xE0 ; 224 24a: 9e 42 sbci r25, 0x2E ; 46 24c: 90 f5 brcc .+100 ; 0x2b2 <__vector_15+0x98> inverse_velocity_overflow += 1500; 24e: 80 91 d3 02 lds r24, 0x02D3 252: 90 91 d4 02 lds r25, 0x02D4 256: 84 52 subi r24, 0x24 ; 36 258: 9a 4f sbci r25, 0xFA ; 250 25a: 90 93 d4 02 sts 0x02D4, r25 25e: 80 93 d3 02 sts 0x02D3, r24 if((inverse_velocity_overflow >= 3000) && ((inverse_velocity_overflow - 1500) > encoder.inverse_vel)) 262: 80 91 d3 02 lds r24, 0x02D3 266: 90 91 d4 02 lds r25, 0x02D4 26a: 88 5b subi r24, 0xB8 ; 184 26c: 9b 40 sbci r25, 0x0B ; 11 26e: b8 f0 brcs .+46 ; 0x29e <__vector_15+0x84> 270: 80 91 d3 02 lds r24, 0x02D3 274: 90 91 d4 02 lds r25, 0x02D4 278: 20 91 02 01 lds r18, 0x0102 27c: 30 91 03 01 lds r19, 0x0103 280: 8c 5d subi r24, 0xDC ; 220 282: 95 40 sbci r25, 0x05 ; 5 284: 28 17 cp r18, r24 286: 39 07 cpc r19, r25 288: 50 f4 brcc .+20 ; 0x29e <__vector_15+0x84> encoder.inverse_vel = inverse_velocity_overflow - 1500; 28a: 80 91 d3 02 lds r24, 0x02D3 28e: 90 91 d4 02 lds r25, 0x02D4 292: 8c 5d subi r24, 0xDC ; 220 294: 95 40 sbci r25, 0x05 ; 5 296: 90 93 03 01 sts 0x0103, r25 29a: 80 93 02 01 sts 0x0102, r24 } else encoder.inverse_vel = inverse_velocity_overflow; L1_OFF 29e: 2b 98 cbi 0x05, 3 ; 5 } 2a0: 9f 91 pop r25 2a2: 8f 91 pop r24 2a4: 3f 91 pop r19 2a6: 2f 91 pop r18 2a8: 0f 90 pop r0 2aa: 0f be out 0x3f, r0 ; 63 2ac: 0f 90 pop r0 2ae: 1f 90 pop r1 2b0: 18 95 reti if(inverse_velocity_overflow < 12000){ inverse_velocity_overflow += 1500; if((inverse_velocity_overflow >= 3000) && ((inverse_velocity_overflow - 1500) > encoder.inverse_vel)) encoder.inverse_vel = inverse_velocity_overflow - 1500; } else encoder.inverse_vel = inverse_velocity_overflow; 2b2: 80 91 d3 02 lds r24, 0x02D3 2b6: 90 91 d4 02 lds r25, 0x02D4 2ba: 90 93 03 01 sts 0x0103, r25 2be: 80 93 02 01 sts 0x0102, r24 2c2: ed cf rjmp .-38 ; 0x29e <__vector_15+0x84> 000002c4 <__vector_28>: L1_OFF }

So we have 7 push, 7 pop, 1 eor, 1 in, 1 out and 1 reti. Also we can subract the sbi and the cbi.

So I get 14*2 + 1 + 1 + 1 + 5 - 4 = 32 clock cycles.

And finally

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before

the interrupt is served.

So I I assume worst case of interrupting a 5 cycle instruction then I would at 4 cycles for the instruction to finish + 5 + 3 = 12 more cycles.

So putting it all together the max time this will take would be for 12 MHz is 4.92 + (32+12)/12 = 8.6 us.

Can someone please confirm that I am doing this correctly?