Using mega128a & trying to spit out simple test...xtal 14.74x MHz, all initialized ok for 9600-8-n-1
outreg ubrr0h, zero ldi temp, uart_speed ;set to desired UART speed outreg ubrr0l, temp outreg ucsr0a, zero ldi temp, (0<<rxen0)|(1<<txen0)|(0<<rxcie0) ;enable rx,tx, isr functions outreg ucsr0b, temp ldi temp, 06 outreg ucsr0c, temp
I have the following loop:
holup: inreg temp, UCSR0A SBRS TEMP, UDRE0 rjmp holup ldi temp, 'W' outreg UDR0, temp RJMP HOLUP
It tends to spit out garbage unless I add some sort of delay (then it works fine)...its as though udre is not working properly or the chars are too close together...they seems right on top of each other....should udre keep the stream spaced out enough? The level shifting looks good...never ran into this before..I hate to add delay without knowing, since this seems quite strange