256 bit shift register required

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ADD bitbyte_old,bitbyte_old 

Should have been

LSR bitbyte_old,bitbyte_old

to get the bit's out in correct order :)

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There is nothing like

LSR bitbyte_old,bitbyte_old 

And you cannot shift right with add operation. I suppose what you wanted to do was:

Quote:
lsl bitbyte_old

Yes, your idea is even better. You still could do it shorter and, what is more important, have the return value in SREG_C.

Bitshift_f:
   lsl    bitfield
   sbic   PINA,6               ;check argument
      inc   bitfield      ;(****) 
   brbs   SREG_C,reload_data      ;7/8 
   lsl    bitfield_old
ret

I did not simulate it, but it seems ok. This gives 5 clks + reload (I suppose about 14 clks), which will be about (7*5+1*14)=6.125clks on average. This gives 382ns!!.

But look at this one:

Bitshift_f:
   rol bitfield
   brbs SREG_C,reload_data
   rol bitfield_old
ret

Takes the argument in SREG_C and returns the argument in SREG_C, and runs even faster. I wonder why I did not notice it earlier, it looks so simple. And what is more important, (7*3+1*12)/8=33clks which gives 258ns!!. Cannot do any better

No RSTDISBL, no fun!

Last Edited: Tue. Jun 1, 2010 - 03:31 PM
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Quote:
And you cannot shift right with add operation

A avr don't have the LSR instruction !!!
is a ADD rn,rn.

I was just not sure if I had to shift left or right to get the bit order correct :)

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"LSR x" is not "ADD x,x"!!!

No RSTDISBL, no fun!

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sorry LSL is, and that was what I want to use ! other wise you need to init with 0x80 and not 0x01

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Sure thing, LSL is. I guess this buffer shift cannot be made faster. I wonder how to write it in C, not using asm(":::") statement :)

No RSTDISBL, no fun!

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And there is one more thing. Both shift registers could be used in one register, if we were able to countdown 8 times. For example in external loop, because this function will be called by some loop for sure. If the loop works around 8, then all the necesseary code would be a simple
"rol bitfield" and reload once every 8 bits.
Reload would be a simple:

      st   X+,bitfield
      andi   byte_pointer_H,BITSHIFT_MODULO_MASK
      ld   bitfield,X 

There is not much to be done.

No RSTDISBL, no fun!

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I have not simulated it but I think that you will have a problem with the aligment of the two set's of bit, if you try to make them as one (carry in and out have a delay of 8 clk!)

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- On the first iteration we put SREG_C in lsb.
- On eighth iteration mentioned SREG_C is in the msb position. We save the byte.
- Afterwards we modify the rest of the pool: EXP2(N)-1 bytes of the loop (EXP2(N)-1)*8 bits actually.
- Afterwards we load our old byte and at the msb there is our buddy - we push it out as the first one. EXP2(N)*8 bits. Delay is fine(It seems :).

There are fifos and Lifos. Fifo has the advantage it can be built pushing and popping in one function. An example is "ror". Lifos are not that pretty. Pushing and popping must be placed into separate functions. Anyway, this is a subject for another post.

No RSTDISBL, no fun!

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Now I remember why that way is a problem on a AVR (it's commen on about all other) is that it's hard to get a bit into C

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What do you mean by

Quote:
hard to get a bit into C

It is hard to put data in SREG_C or it is hard to manipulate bits in ANSI C?

No RSTDISBL, no fun!

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