Cycle stealing Xmega DMA Effective ?

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For xmegas that have DMA, I don't get HOW it's faster / advantageous since it's cycle-stealing and doesn't have its own data bus. Why not just use the CPU ( since it can't be used if DMA's used, and so is idle -- then in it's idle state for other tasks -- use it to move whatever data one has )?

1) Studio 4.18 build 716 (SP3)
2) WinAvr 20100110
3) PN, all on Doze XP... For Now
A) Avr Dragon ver. 1
B) Avr MKII ISP, 2009 model
C) MKII JTAGICE ver. 1

Last Edited: Mon. May 25, 2015 - 03:24 AM
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dma vs interrupt - dma has no interrupt overhead, it can increment the source/dest address and decrement the count. How many cycles does it take to do that in an ISR? It is not the solution for everything, but can do specific tasks faster.

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Right, but what if don't need ISR ? If i can do a blk. data move with DMA, CPU MUST be idle. So use it ( CPU ) then for the move anyway. Where's performance (+ ) for using DMA in that case ?

1) Studio 4.18 build 716 (SP3)
2) WinAvr 20100110
3) PN, all on Doze XP... For Now
A) Avr Dragon ver. 1
B) Avr MKII ISP, 2009 model
C) MKII JTAGICE ver. 1

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I have the ADC sampling with 2MHz and the 12-bit data
is written into an array with 2 Mega Samples/sec.
I think that would not be possible by using instructions.

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Quote:
If i can do a blk. data move with DMA, CPU MUST be idle.

The cpu doesn't necessarily need to be idle. Suppose, for example, you are using DMA to transfer data between SRAM locations. As long as the cpu is executing instructions that just access registers, IO memory, external memory, or EEPROM, then the transfer can occur simultaneously.

If DMA is used to transfer between SRAM and IO memory, then the cpu can still access registers, external RAM, and EEPROM. The problem in this case, it seems to me, is that if the instruction needs to access the status register or stack pointer (and many of them will), then the accesses cannot occur simultaneously because both these registers are located in IO memory. I would expect most people to use DMA for this type of transfer. In my opinion, the IO memory REALLY needs to be accessible by DMA without the cpu blocking access because of frequent status register updates. But, I may be wrong about this limitation. It would explain the considerable delays I often experience when using DMA to transfer from SRAM to the SPI data register.

https://www.mattairtech.com/
ARM Cortex M and XMEGA development boards / Gentoo Linux

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I posted this and found you. Think you would help me on this.

I am programming on AVR alxmege128a1 xmegaPlain board with AVR Studio. The currnt task is to program DMA triggered from USART SPI Master mode. I made the USART worke on its SPI Master mode talked to a SPI slave. I also saw the trigger from the source of USARTD0 on the Receive complete (RXC) work partially but not fully work as expected. basically the trigger fired and recive in the DMA interrupt handler but did not read the right data from the USART reciving data suppose.

I like to provide sample code if get some helps sinitially.

Thanks,
Chester

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Ross McKenzie, Melbourne Australia