I've read in the pdf that reading a port takes some cycles, but nothing related about output.
How much time does it take? 1 cycle like other instructions?
That depends on the instruction. The datasheet has a table for the instruction set summary that specifies the number of clocks for each opcode.
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What does the datasheet say about the number of cycles needed for an IN? and an OUT? and SBI and CBI?
Which PDF? Give a quote about "reading a port takes some cycles" so we can have some context. Why does the answer matter to your app? Are you concerned about sub-cycle timing?
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For any instruction, the output apparently changes within the time THAT instruction is being executed. Seems to me there is a timing chart in the I/O section. The delay (from the start of instruction execution to pin change) will be different for different instructions having different number of clock cycles, but you should be able to expect it to be consistent for any given instruction.
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I suspect the OP is referring to the latch
that one reads when reading a PIN register.
IIRC it delays by a cycle the moment an externally imposed
voltage can be read by software as a new bit value.
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I mean input/output and latches.
For input, there is a timing diagram in the pdf, but nothing for outputs. So I supposed, output is atomic?!
For input, there is a timing diagram in the pdf,
I see an explanation under Reading the Pin Value in the Mega324PA datasheet, for example. My brow furrows and I think "So what?" Why does it matter to you? The only time it might come into play in an AVR app is doing a read-back of PINx after a write to PORTx, for pullup or otherwise to see if the output is pulled low. And then you have to have one NOP. In hundreds of AVR apps I don't remember it ever coming up in practice. But there are those that like to model AVR port behaviour trying to get a perfect SPICE model. Those people just don't realize that the world consists of nothing but 1s and 0s and "analog" is yet another invention of the Flat Earth Society.
Assuming 16mhz clock (62.5ns), a hi output should pull down in 62ns. I think.
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When switching between output and input, I found 2 cycles were needed at 20MHz in order to read the port data. I use 3 NOPs just to play it safe.
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There must be some propagation time internally and some pulse rising time relating with the parasitic capacitance of pcb traces and the other circuit.Clocking in higher CPU speeds one or more nop instructions allow output to reach its voltage limit before any pin reading.
The rise/fall time of a port pin as an output is in the neighborhood of 10ns if not heavily loaded with capacitance. So, that is small compared to a 50ns clock cycle at 20MHz.
Going from input to output should be fast, because drivers are getting turned on. Going from a low output to input with pulluo is a different matter. The equivalent pullup resistance is pretty large so it takes very few pf to cause a long rise time. In this direction, you can easily get a rise time longer than a clock period.
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