Mislabeling (possible misinterpretation) of interrupt option

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#1
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Hi,

In AVRStudio (4.18, build 684), there's a mislabelment of the options of the interrupt sense system of an ATMega32.

Also, may be misinterpreted by the simulator - it's acting really freaky, and the code is correct (works on real system). See screenshot for more info.

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There are pointy haired bald people.
Time flies when you have a bad prescaler selected.

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I can't help noticing that in ATmega32.xml in the ../PartDesciptionFiles directory it has this:

        
          ISC10
          Interrupt Sense Control 1 Bit 0
          The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set.The level and edges on the external INT1 pin that activate the interrupt are defined below.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC11:ISC10) Description: (0:0) The low level of INT1 generates an interrupt request. (0:1) Any logical change on INT1 generates an interrupt request. (1:0) The falling edge of INT1 generates an interrupt request. (1:1) The rising edge of INT1 generates an interrupt reques
          RW
          INTERRUPT_SENSE_CONTROL
          0
        
        
          ISC01
          Interrupt Sense Control 0 Bit 1
          The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt request
          RW
          0
        
        
          ISC00
          Interrupt Sense Control 0 Bit 0
          The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt request
          RW
          INTERRUPT_SENSE_CONTROL
          0
        

It seems "odd" that BIT1 has no tag - wonder if this matters ?? ;-)

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I

Quote:
t seems "odd" that BIT1 has no tag - wonder if this matters ??

I don't believe so since this text description has nothing to do with what is showing up in the GUI. In looking at similar things with other bit collections such as the SMx bits, it seems that the enum is always only stated in the LSBit description.

The ISCx bits also appear under CPU, and there the options are defined correctly. It uses a different enum (INTERUPT_SENSE_CONTROL2).

Quote:






...






Certainly this incorrect enum definition is not going to cause improper behavior.

Regards,
Steve A.

The Board helps those that help themselves.

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Well, something does seem to be causing improper behaviour - the program kept jumping to the interrupt over and over, since the pin was on low state. In reality, it worked perfectly - only on log. change goto interrupt.

There are pointy haired bald people.
Time flies when you have a bad prescaler selected.