AVR Freaks

Likewise, I am confused about what you are trying to do.

Are you measuring amplitude or time interval? What events denote the edges of the time interval, if that is what you are doing? What is the problem with the multiplexer you are now using?

Jim

So, why not, in a fast loop, just make the output bit the 'OR' of the 8 input bits?

If your clock is, say, 8MHz, you should be able to do such a loop in a few microseconds, maximum. that would be under 0.1% of the nominal pulse width.

Jim

That would assume all the signals are "out of phase" and non-overlapping. That might indeed be the case if the origin of the signals is a "soft multi-channel hobby servo driver" as is often discussed here, but if these are independent then there might be overlap.

And if there is a lot of overlap, then there could be a few microseconds of jitter on the channels.

What needs to be decided here is the precision and accuracy needed. The signals are slow so a few microseconds shouldn't matter.

So you make an output "driver" using compare match with timer1, and have timer1 free-run. You have an output array of how many timer1 counts each channel should be high. Then you march through that array and set the OCR register accordingly, and then do it again for the next one. The dead time and the inter-cycle gap are left as exercises for the student.

On the input side either a very fast poll (if debouncing needed) or interrupt pins can be used. When a transition is seen the TCNT1 is trapped and stored as the beginning or ending count. When the ending count is seen, the subtraction is made and the array entry for that channel is updated.

Lee

A agree. A simple 8-in OR gate would seem to provide all the function needed.

Jim

I assume that the OP wants to demultiplex the signal at the other end of the wire, whatever and whereever that may be. What he is describing is essentially time multiplexing of signals.

The solution here may be to use an SPI interface as a hardware serializer. You can run the clock rate on that pretty high (system clock divided by 2 is the max, I believe) and then you have cut your compute load by a factor of 8. Actually, a little higher, since you will need to signal the receiver somehow about beginning/end of the time slot. So, either toggle or cycle the /SS signal to indicate the end of one frame and the beginning of the next.

It's just an idea.

Stu

Sigh. Didn't I first say:

So give some numbers.

Lessee-- 2us allowance on a 2ms pulse width-- 0.15 tolerance, and 8 channels. That will be quite difficult if not impossible with the microcontroller model chosen. Lessee--timer1 has to span 2ms so that's 30ns/tick; /1 at 20MHz is 50ns.

An interrupt-driven approach would "work" but introduce too much jitter when there is any interrupt latency due to another event. And on that model you would have to scramble to get eight edge-interrupt sources unless you use a bank of pin-change. That would be OK, I guess, but you still have a jitter problem if the output ISR overlaps the input event.

The above is really a shame as there are so few events to handle overall--like a couple each millisecond.

A tight loop with a port read and TCNT1 read and then make your own "pin change" masking might work OK. Yep, I think that would work. You'd only get jitter when multiple input pins change during the same "read"--unlikely.

Now, if you want to do it "right"--use an Xmega. Even the A4 has plenty of input-capture channels, and timer(s) left over for the output. Given the slow pulse speeds there should never be any races. Yep, a perfect example of the Xmega being able to do the job that classic AVR8 finds difficult/impossible.

Lee