XMEGA EEPROM endurance

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I know that there were already some threads concerning the flash write/erase endurance (which aren't answered yet)...

Anyhow I like to know if someone can say something about the EEPROM endurance. In ATmega data sheets you can always find an endurance of 100000 write/erase cycles.

Can I assume that the EEPROM endurance of the XMEGAs is the same or even better? I am not sure about it, because the chip is completely redesigned.

BTW: 100000 write/erase cycles would fulfill my requirements.

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I guess it's the same as the standard AVR endurance as Atmel likely uses the same non-volatile memory technology and won't invent a new technology for a spin-off series.

If they did, they certainly would mention it with a lot of marketing fluff :)

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We've been there [same question] before. ;) Ask Atmel and let us know the answer.
https://www.avrfreaks.net/index.p...
https://www.avrfreaks.net/index.p...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Lee,

you are right concerning the previous threads. But they are all about the flash endurance. I would like to know something about the EEPROM endurance.

However I have opened a ticket in the Atmel support. I will let you know about the results.

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Quote:
BTW: 100000 write/erase cycles would fulfill my requirements.

How about 80,000 EEPROM Write/Erase cycles?

The XMega A3 Data Sheet, Table 34.4 Flash and EEPROM Memory Characteristics notes a minimum of 80K cycles at 25'C, 30K cycles at 85'C.

JC

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Wow, I am again surprised at how the Xmega doesn't seem to use "proven" Atmel subsystems.

-- JC now showed where the EEPROM is a downgrade in endurance from AVR8.
-- The EEPROM is also royally screwed up on many of the Xmega series, nearly to the point of unusability.
-- There are a whole passel of problems with the 12-bit ADC. That is proven technology in the ARM SAM7 series.

When I saw the Xmega announcement, I figgered it would be fast to market. The I/O and interrupt system and peripherals looked a lot like the SAM7. The clock rates corresponded to the max flash rates of the SAM7. So bolt those subsystems onto the proven AVR core and off you go. (Why they didn't offer MAC or otherwise enhance arithmetic operations for "8/16 bit" is a mystery to me.) Voltage levels are about the same as SAM7.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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DocJC wrote:

How about 80,000 EEPROM Write/Erase cycles?

The XMega A3 Data Sheet, Table 34.4 Flash and EEPROM Memory Characteristics notes a minimum of 80K cycles at 25'C, 30K cycles at 85'C.

80000 would also be enough. But actually I am using an ATXMEGA128A1. And I didn't found anything corresponding in the A1 data sheets.

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CE,

I agree, I do not find any mention of the EEPROM's cycle life in the A1 data sheets!

If you are not using all of the peripherals of the A1 then perhaps the A3 version would be a possible alternative.

I think you should contact your Atmel Rep and point out the absence of the EEPROM table in the A1 data sheets, ask for the specifications on the A1 series, and suggest that their "Preliminary" data sheet needs updating!

JC

Note that the XMegas are otherwise pin and code compatible throughout the series.

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DocJC wrote:
If you are not using all of the peripherals of the A1 then perhaps the A3 version would be a possible alternative.
You are right, the A3 series is an alternative, but it came too late for my project.
DocJC wrote:
I think you should contact your Atmel Rep and point out the absence of the EEPROM table in the A1 data sheets, ask for the specifications on the A1 series, and suggest that their "Preliminary" data sheet needs updating!
This is what I did and I just got the answer tonight. Here it is:
Quote:
EEPROM endurance parameter is similar for all XMEGA devices, we are expecting the datasheets to be updated with the appropriate values soon on web.

EEPROM:
25°C 80K- Write/Erase cycles
85°C 30K- Write/Erase cycles

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DocJC wrote:
Note that the XMegas are otherwise pin and code compatible throughout the series.

Perhaps not 100% code compatible, since some opcodes require different clock cycles. So if some assembly code relies on exact timing, you would need to modify the code. For example, the SBIC opcode takes 1/2/3 cycles on a regular AVR, but 2/3/4 on the XMEGA.

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Hi Ganzziani,

I may not have stated the above very clearly.
It is my impression, (As a Bascom Bit Basher, not an Asm programmer!), that within the XMEGA series the chips are pin layout and code compatible. The difference being in the number of peripherals on the various chips, as well as the amounts of the various forms of memory. I agree, they are totally different pin and code wise from the Tinies and Megas.

CE,
Thanks for posting the Atmel response.

JC