As I understand, each GPIO port with 32 GPIO pins should have one IRQ, right?
UC3B should have two GPIO ports, so it's AVR32_GPIO_IRQ_0 and AVR32_GPIO_IRQ_1 that are used, right?
then how about AVR32_GPIO_IRQ_3, AVR32_GPIO_IRQ_4 and AVR32_GPIO_IRQ_5?
are they not used by anything?
Hello,
yes each port has one IRQ.
Yes UC3B should have two (= and1) only.
They (2..5) are prepared for other models like UC3A0 with or without EBI and PortA, B, C and PortX but should not appear within an UC3B docu.
ok, but they are in the document,
UC3B datasheet Rev.G pp35, you can see them in the list.
And in the file uc3b0256.h in the section for GPIO:
#define AVR32_GPIO_IRQ_0 64 #define AVR32_GPIO_IRQ_1 65 #define AVR32_GPIO_IRQ_2 66 #define AVR32_GPIO_IRQ_3 67 #define AVR32_GPIO_IRQ_4 68 #define AVR32_GPIO_IRQ_5 69
I found them on page 35 too and I think that Atmel has somehow generated the headerfiles.
so are they useful or not?
As far as I understand the data sheet they are not useful because you can't trigger them.
ok, thanks then.
each port has one IRQ.
so you mean every 8 GPIO pins share one IRQ?
So is the connection like this?
GPIO 0 ~ 7 -> AVR32_GPIO_IRQ_0
GPIO 8 ~ 15 -> AVR32_GPIO_IRQ_1
GPIO 16 ~ 23 -> AVR32_GPIO_IRQ_2
GPIO 24 ~ 31 -> AVR32_GPIO_IRQ_3
GPIO 32 ~ 39 -> AVR32_GPIO_IRQ_4
GPIO 40 ~ 43 -> AVR32_GPIO_IRQ_5
Hello,
yes it is. You can find it in chapter 20.4.6 on page 156. And that's it why UC3A has 14 interrupts. Four for each PortA and PortB, one for PortC and five for PortX.
I beg your pardon about that mistake on my side.
ok, i see it now.
now I understand.
correct :)
ok, thanks.
