## timer1 with prescaler

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I might (???) have encounterd a problem with timer1:

I use timer1 in the compare capture mode. Setting the prescaler to "8" and given, the compare match would occur at "3", the counter would generate the following sequence:

00000000 11111111 22222222 3 call ISR

as in, the ISR would be called after the 25th cycle!?

After the occurance of the first overflow - and for all future events - the counting pattern would be:

0000000 11111111 22222222 3 call ISR

and that's ONE cycle less.

Am I right or wrong??? Does it really mean a "problem". I'm generally interessted in solving that problem and addressed it to Atmel directly via their internet page, but no response (yet?)

Chris

This seems correct to me.

When the counter starts, the prescaler counter is also started (3bit counter when prescaler = 8) The prescaler counter is 000, and hence eight cycles will have the timer value 0 (takes eight cycles before the prescaler counter reaches 000 again.

The clear on compare match feature clears the timer when the value 3 is reched, but the prescaler is not cleared, ie the prescaler counter is 001 when the timer clears, and hence the timer is only 0 in seven cycles (time taken before prescaler counter again is 000).

The count sequence is |C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0,0 | 1,1,1,1,1,1,1,1|...
This way there will always be 3*8 = 24 cycles between each interrupt (except for the first
interrupt where the counter will count 25 cycles before compare match)

The newer AVRs (ATmega161/ATmega163) have a count secuence as indicated below
C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|... (according to their datasheets)

The main difference is that in old parts you have to compare with 3 to get 24 cycles between interrupts, and in new parts you compare with 2.

hope this clarifies.
rgds
Bjorn