access to program counter via jtag

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#1
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Hi
Sorry because I'm beginner.
I want to know how to access PC Reg value by JTAG interface without using AVR studio .
Actually I need to read PC Reg value with sequential circuits because of fault tolerant problems.
I need JTAG(or OCD) instructions to do it.
thanks for your time and your help.

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Well you could use avr-gdb (possibly hacked up for your purposes) and a JTAG ICE debugger to do this. If you want to do this from some other micro, you're going to have more work to do. I am unsure as to whether there are any open source JTAG ICE debugging clones, but if there are, they would probably be your best bet. Atmel only releases the JTAG debugging protocol to select vendors, making the task a rather interesting problem. I'd say it might be time to break out a logic analyzer, sniff the JTAG lines, and start reversing!

Math is cool.
jevinskie.com

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I believe the specific JTAG instructions are in the datasheet.

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atomicdog wrote:
I believe the specific JTAG instructions are in the datasheet.

As far as I know, only the memory programming commands are given out publicly. The datasheet for my AT90USB1287 lists all the OCD instructions as "private".

AT90USB1287 Datasheet wrote:
PRIVATE0; 0x8
Private JTAG instruction for accessing On-chip debug system.

Math is cool.
jevinskie.com

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Quote:

Well you could use avr-gdb

By that I guess you really mean use 'avraice' or just study its source code? It's the thing which provides the Atmel/AVR/JTAG specific interface to the generic GDB.

Clearly the source of avarice must expose the communication protocol it is using to interact with the JTAGICEmkII (via libusb APIs I guess?)

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thanks all
but I need to do this with minimum Hardware super addition .I wanna implement that with sequential circuits.then I can't use personal computer and any tools
such as JTAGICEmkII ,... .

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Quote:
Clearly the source of avarice must expose the communication protocol it is using to interact with the JTAGICEmkII

So you mean I have to decompile (or disassemble) the softwares like avr studio , avrice ,...

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Quote:

So you mean I have to decompile (or disassemble)

No. There are many ways to develop for the AVR and most are commercial with closed source code so all you get are binaries.

But there is an open-source development system for AVR with the compiler provided by GCC, the binutils from GNU and various other tools from various sources - most of which are hosted at SourceForge.

"avarice" is just one component of the overall GCC/AVR-LibC development and it's source code is open at:

http://sourceforge.net/projects/...

You'll notice that two of the authors listed there (arcanum, joerg_wunsch) are actually regulars here on Freaks (EW, dl8dtl).

Perhaps the easisest way to get the source is to visit:

http://avarice.sourceforge.net/

and take a copy of the daily CVS snapshot. You'll notice lots of lovely jtag*.c files in there!

Cliff

EDIT: by the way, looking at the .bz2 the doc/avrIceProtocol.txt is VERY VERY interesting! (it's documentation of reverse engineering the protocol between Studio and the JTAGICEmkII)

EDIT2: there's also an interesting note in doc/todo.txt that says "Atmel have now published the protocol in AVR060 - a very confusing document" but maybe it should be read in conjuction with EDIT1?

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It seems to be useful.
Thank you so much Dear clawson.

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I am a little puzzled by what you mean by "simple sequential circuits". If you mean gates and latches, then you have a REALLY big job that would be best done in something like a CPLD.

This is really of the scale that warrants another micro.

You refer to "fault tolerance". Are you thinking of looking for an out of bounds PC and forcing a reset by the external circuit?

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Hi Jim

Quote:
what you mean by "simple sequential circuits"...

I mean i don't want to use any micro or PC, Actually I wanna implement it with FPLDs for testing and simulating.
Theoretically : at final it must be implemented on real silicon chip .
Quote:
You refer to "fault tolerance"...

This is simple project for University "fault-tolerant systems" study :
If any fault occurs in program counter(specially in jumps),I want my Hardware to recognize it and makes a decision. at all it doesn't matter now.
Thanks for your patient.

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How will the FPLD know where the PC is supposed to be at any instant in time? Surely it's going to require a copy of the same code and a complete simulation of the AVR core to run it on? Anyway what makes you think a JMP would ever fail? I can see how cosmic activity can cause a RET to fail (because electrons in the stored return address in SRAM have been bombarded) but JMP's a re hard coded in flash. Surely the only way they can go wrong is if the core is hit after the opcode fetch but before PC is reloaded?

This all seems like an exercise in futility. If you want to make something faut tolerant consider the research the satellite guys have done where all the problems of sending electronics into (fast particle) space have already been considered/analysed.