Can vias short to components' bottom side?

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It's occurred to me recently that I run a lot of vias under USB connectors, SD card holders -- even my MCU (which has a ground pad underneath, unused since I'm hand-soldering and the datasheet indicates that it's optional). Is there any real danger of those vias shorting to the surface above them? I am (I think) sending my board designs off with vias to be fully tented, but even at that they seem to often come back half-showing. Should I be taking some kind of precaution to prevent shorting, or is this just paranoid?

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If the vias are in signal or power lines then I think you have a problem. Especially if the MCU has a ground pad underneath. Well, is it a heatsink pad or actually connected to the MCU -ve supply rail? Even if it is just a heatsink pad it could short out one via to another. If they all go to ground then maybe not a problem.

If you have a solder resist coat over all the vias then you are probably OK putting components over them, but something metallic and at a different potential . . . I'd be thinking about it again.

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It is well known that traces or vias under a quarz-
crystal may pose a problem. But there are isolation
pads:

http://www.digitallehrer.de/cms/...

I remember that we used a sort of signal-isolation-
transformer. In the first production run it had
a plastic mounting plate, but in the second
run it had a metal shielding base that perfectly shorted some of our PCB traces by contacting vias.

So I learned my lesson.

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I'm also curious about this issue. For the QFN64 AT90USB647, I've been using something like the attached image. I've shrunk the actual bottom pad, which gives me a bit of space to route traces and vias under the chip.

The vias here in the image are for power and signal, so they would definitely cause problems if accidentally shorted to the bottom pad of the chip, which spans the entire space between the outer pads, and is internally connected to ground.

Reading this thread, I'm concerned that vias which aren't completely covered by the solder mask could cause hard-to-diagnose problems. Although the vias are supposed to be tented, the solder mask is never really perfect. Aiming for a "production quality" product, would you guys avoid putting vias like this under a chip, or is it kosher?

Michael

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QFN puts more thermal stress on the joints than TQFP. Sometimes it is advised to solder the pad underneath to allievate that problem.
My preference would be to have no vias under the chip so that it sits pretty for soldering. However, I'm no expert, although that last beer seems to have made me so -til tomorrow!

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Yeah, I've learnt my lesson there also for some Aluminum heat sinks on to220 components shorting to a top side gnd plane.

I'd certainly avoid it. When you do mass production of anything the probabilities tend to play out. As you say soldermask is never perfect, relying on tented vias probably isn't smart thinking.

oddbudman

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Relying on solder mask for isolation, whether on a via or a trace, is not a good idea. It is not intended for that.

Stealing Proteus doesn't make you an engineer.

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ArnoldB wrote:
Relying on solder mask for isolation, whether on a via or a trace, is not a good idea. It is not intended for that.

Is there something that is? Can isolation pads such as those ossi mentioned be cut to other sizes? Alternatively, is there a reasonable solution for a hobbyist looking to produce a one-off (a coating or something that can be used to provide isolation)?

I'm going to take a shot at rerouting my board such that there are no vias (or anything else besides ground) under the MCU and SD card, but I have doubts about that being manageable without using a larger enclosure, given the real estate the two of them take up...

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There are isolation pads you can get, and kapton tape can be applied in manufacture, but you are FAR better off to not place the vias under components that could be a short problem. (metal cases)

You could hit the vias with paint or nail polish before you mount the components as a short term workaround.

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Thanks. I'm going to take a solid crack at the no-via solution before I go to anything else.

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OR you could use buried via's for those that might pose a risk. I often place via's under plastic packages, but I have never done so on a package with a thermal pad. I never had to use buried via's either, and would try to avoid them whenever possible, due to the higher cost of board and difficulty when debugging.

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I have used vias under thermal pads where electrical contact (and thermal conduction) is needed.

Most devices with back-side thermal pads REQUIRE soldering to the thermal pad. Never seen any optionals, but there is a first time for everything.

Usually, solder mask is thick enough so that you could not readily contact a via with a flat surface. However, solder mask is also a bit brittle and I would not rely on it for a long time interval.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Managed a board layout without any vias under the MicroSD holder, the AVR, or the crystal (attached). This is my second iteration on my first AVR project -- looking forward to seeing how it works. Thanks again to everybody who responded!

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simple rule: never place traces or vias under unused/unconnected pads, or conductive surfaces.

If you must break the rule, then make sure you take necessary precautions to prevent potential shorting down the road. Simple mechanical vibrations over time can erode the LPI mask exposing the trace or via.

Also note that the copper can be exposed in the LPI along any edge of the copper. This is due to the sharp vertical change in elevation on the board surface. The problem becomes more pronounced with heavier copper weights. This edge is also where the erosion of the LPI happens the quickest.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

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For whatever it's worth, this is what the Butterfly board looks like after the mega169 has been removed. I'm not a hardware expert so I don't know exactly what I'm looking at. The board is a different color there, so maybe they slapped on a coat of blue paint. :)

The Butterfly uses the MLF/QFN package.

I presume they bake these boards in an oven, and I don't know how they avoid the stresses due to uneven thermal expansion. This board is half the thickness of the other boards I've looked at. I suppose that would allow this board to stretch easier than normal boards.

Before I put a chip with more memory on there, I wick up the solder that the manufacturer puts on the big pad in the middle of the chip. I don't know if it is necessary though.

Actually I wick up that bleepin' lead free solder from all the chip's pads, but that's another story. :)

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