sink source question about general i/o pins

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Is it true that a general i/o pin on the ATMEGA can both sink and source current up to 40mA?

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What does the datasheet say?

(my understanding was 20ma - but some devices may differ)

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spoetnic,

There may also be port limits.

ie. Each pin may sink or source 20ma but the whole port can not exceed 100ma.

A

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Quote:

What does the datasheet say?

(my understanding was 20ma - but some devices may differ)


... and "ATMEGA" is too broad--do you expect a blanket answer over differnet generations from original Mega103 through early Mega8, Mega163 through the current generations Mega___PA?

There are also limitations per port and per "chip section".

It is strange that you would ask this question without looking at a datasheet. In fact, even for this old bit pusher when I pull up a datasheet for any device I think one of the first things I look for is the "Electrical Characteristics" or similar section and look at voltages, currents, and timings.

-- In general, most I/O pins on most Mega models will have symmetrical sink/source.
-- The 40mA you mentioned is the Absolute Maximum Rating on many models. Do you really want (or intend to) run right at the edge where you can damage the chip?
-- Have you looked at the curves of "Pin Driver Strength"?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Off course I did look into the datasheet. I refer to the ATMEGA32 datasheet. On page 50, where a general i/o port is sketched, it wasn't really clear if it was both sink and source. I am used to the 8051 architecture, where only sinking is possible (up to 20mA).

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Quote:

Off course I did look into the datasheet. I refer to the ATMEGA32 datasheet. On page 50, where a general i/o port is sketched, it wasn't really clear if it was both sink and source. I am used to the 8051 architecture, where only sinking is possible (up to 20mA).

In my copy of the mega32 datasheet the Electrical Characteristics section actually begins on page 285 but if your question was actually "is it really symmetrical?" rather than what the exact levels were the answer is "yes". This is one of the attractive features of AVRs.

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Quote:

where a general i/o port is sketched, it wasn't really clear if it was both sink and source.

Did you look at the real specs in Electrical Characteristics and Typical Characteristics rather than just the "sketch"?

Did you look at Pin Descriptions where it says for each port

Quote:
The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability.
?

When you were looking at the sketches on pages 49 and 50, did you read the first paragraph of that section where it says

Quote:
Each output buffer has symmetrical drive characteristics with both high sink and source capability.
?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I don't think the datasheet directly answers OP's question.

Quote:
Is it true that a general i/o pin on the ATMEGA can both sink and source current up to 40mA?

The datasheet does give 40mA as the absolute maximum "DC Current per I/O Pin." That tells us > 40ma is definitely taboo. Good practice says 39.9 is a really, really bad idea. What about 27ma? What if VCC is 3.3V? The absolute max spec doesn't differentiate.

It then goes on to give VOL and VOH levels at a particular test condition current (20ma, 10ma for 5V, 3V respectively). It then goes on to say

Quote:
Although each I/O port can sink/source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) . . . If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. Pins are not guaranteed to sink/source current greater than the listed test condition
I say the answer is that it may be possible, but you shouldn't count on it.

clawson wrote:
"is it really symmetrical?" rather than what the exact levels were the answer is "yes". This is one of the attractive features of AVRs.

I don't see how the symmetrical-ity of the sink/source capability could be feature or design concern. The way I think of it, the pin either has the right v-i curve or it doesn't for what you want to use it for.

When is it important that its sink capability "matches" its source capability?

I agree that high current source along with high current sink is an attractive feature, but the fact that they are equal to each other seems pretty unimportant. Apparently though, the data sheet thinks it is important if it goes to such lengths to declare the sink/source capability as symmetrical.

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As mentioned by the OP, symmetrical is not the norm on x51 so one must design around it.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:
As mentioned by the OP, symmetrical is not the norm on x51 so one must design around it.
For an x51, you might be designing around the sink/source limits, but you aren't designing around the fact that they aren't symmetrical, that is wholly immaterial.