I have a problem with an ATTINY44 not coming out of reset when a slowly rising VCC is applied. The datasheet specifies a 10mV/mS minimum rise time on VCC. However, the design has a lot of capacitance on the front end with a relatively high input impedance. BOD reset is enabled.
Atmel support wasn't much help in providing detailed information on the operation of the POR other than what was already listed in the datasheet.
If the POR doesn't work with a slow rising VCC, could the watchdog timer be made to force a reset instead ? If the WDR was always enabled (with fuse setting), would that force a reset in the event that the POR circuit didn't provide the proper reset due to a slowly rising VCC ?
Has anyone had any experience with this ?