is it possible to have bus contention for FLASH on UC3B?

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hi,

I'm now looking at the HMARTIX section and want to know if it's possible to have bus contention for Slave0 internal flash on UC3B, so that the execution time of my program could be changed in these situations.

But I really can't find any information on UC3B's datasheet about this.

Anyone knows if it will take more than 1 CPU clock cycle to wait for flash?

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anyone knows?

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Depends on your CPU Clock. If it goes above AVR32_FLASHC_FWS_0_MAX_FREQ then you need to set:
AVR32_FLASHC.FCR.fws = 1;

Which gives the FLASHC 1 wait state, then access to flash should take longer than usual.

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yes, i understand this FLASHC speed limit, but I'm wondering if there is any possible bus conflict, that will make this flashc access even slower?

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There should not be flash contention if this slave is only used by the master CPU fetch. Note you can optimize the flash hmatrix access by configuring it in LAST MASTER DEFAULT.

-sma

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ok, but i'm wondering if FLASH slave can connects to other masters? And if so, then other than CPU instruction, which ones can it connects to?

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also meet same problem with you, the flash WP(write page) command seems occupy bus long time, it impacts the DMA and SSC.
Is it possible to priority the DMA and CPU of the BUS usage?

darthvader wrote:
hi,

I'm now looking at the HMARTIX section and want to know if it's possible to have bus contention for Slave0 internal flash on UC3B, so that the execution time of my program could be changed in these situations.

But I really can't find any information on UC3B's datasheet about this.

Anyone knows if it will take more than 1 CPU clock cycle to wait for flash?

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i think so, there is this PRAS0...PRAS15 and PRBS0...PRBS15 registers for setting this.