I'm just starting to tackle (as a hobbyist) CPLDs and FPGAs and will need to learn one of the hardware description languages.
Is there a general consensus pertaining to whether Verilog or VHDL is more appropriate for a beginner? I have extensive programming experience in C, assembler, etc., but none in Verilog or VHDL.
It's largely a matter of taste. Verilog is similar to C and VHDL is based on Ada. Verilog tends to be more popular in the USA and VHDL is used more in Europe.
I find VHDL much easier to use than Verilog.
Xilinx and Altera provide both with their development environments.
Leon
Haven't used Verilog, but VHDL will warp your brain. Just forget every bit of every other language you know (except ADA) and you'll do fine. I'm planning on working on a Ray Tracer with VGA output with my friend on a FPGA over the summer break, programmed in VHDL.
- Dean :twisted:
I started off by learning some basic VHDL and completed a couple relatively small projects using VHDL. I then started to work on a more complex project and was trying to make use of part of a reference design written in Verilog. After reading a tutorial on Verilog I decided I liked it better and have been coding in Verilog ever since.
There were some things that I was finding a bit confusing in VHDL that just seemed simpler in Verilog. Verilog is also more similar to C which made things easier for me.
i think verilog is easier.
and also do not foregt to check this nice site
I prefer VHDL.
Guru Meditation #00000005.00C178A8
Ohh you make me wanna look for my old Amiga :-)
/Bingo
:P
I read few times that teachers had reached a consensus: since VHDL is usually harder to learn, is the teaching language of preference, since it seems that students with VHDL switch easily to Verilog, while switching from Verilog to VHDL seem to be more difficult.
Of course that maked the decission more dark.
I myself use Atmel's CPLD's and Lattice's. For Atmel I use WinCUPL, a development suite that mimics Abel, And for LAttice, I use ispLEVER, another suite that uses Abel.
If I had to choose between Verilog, or VHDL, I would go Verilog
Both are Free
Jim
Here is a wierd answer for you... :wink:
I prefer Verilog, myself. It is just a lot easier to read for me.
However, I would recomend that you learn VHDL first. VHDL is a bit more difficult to use. If you ever get a job that requires the use of VHDL, you might find it difficult to learn after having learned Verilog.
I have to admit I am getting pretty rusty with VHDL, as I haven't used it now for a few years, but I can get back into the swing when I need to.
It aslso depends on how deep into the field you wish to delve.
I would think that you play wit the free tools out there and then take the plunge into th ebig pool
What I am saying, is to use the free tools and a few simple projects and then go for the big stuff
jim
