Strange EMC problem with ATmega324P

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#1
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We have an emission problem with an ATmega324P running with a 16MHz crystal. We get peaks at 32MHz, 48MHz, 64MHz, 80MHz and 96MHz. For some reason the 64MHz and the 96MHz peaks are the highest peaks. They are something like 6dB over the allowed level in the EMC test, the other peaks are well below.

The two layer layout is not very good but the oscillator loop is very small and the oscillator waveform looks good.

This is the first time we have problems of this type so it came as a slight surprise.

Any thoughts on this?

/Janne

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Do the emissions stop, when the AVR is in the RESET
state ? What other signals with fast transitions are
there ?

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The peaks are expected, but obviously the magnitude is an issue. What is the ground plane like around the processor? You may need to put ferrite beads in the power to the cpu.

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Try the clock prescaler settings to see what this is linked to. Proper decoupling for the supplies is a must, of course, but the loads being driven also need consideration.

If you think education is expensive, try ignorance.

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like all said. layout is the problem (some schema perhaps)
send a picture of layout round PCB and schema round PCB. Perhpas can we help.
thierry

Thierry Pottier

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Have you connected the oscillator capacitor grounds directly to the nearest ground pin?

Leon

Leon Heller G1HSM

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It seems as an intermodulation issue of the 16Mhz frequency with a squarewave signal of duty cycle far away the 50% (nearlly 25% or 75% and further). The higher ampiltude of the 4th and 6th harmonic lead to this. If it is not a problem of the particular ATmega324P you have on board, then improve the design

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Thank you for your replies.

Our conclusion is that we need a new layout.

The most confusing thing is what ccharala noted about the amplitude of the harmonics. In my (previous) world the level of higher harmonics was always lower than the level of higher harmonics. Maybe this is just proof of how little I know ;^)

/Janne

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It could also be that the xtal wires form a tuned circuit for thise harmonics. Another reason might be ill sized load caps for the xtal.

Generally the oscillator; XTAL and the two caps should be placed as near as possible to the respective MCU pins. the Ground should form a solid plane under the XTAL and the caps. Keep everything as short as possible. Oh - do not forget to ground the XTAL case if it is metallic.

Making it symmetric also helps.

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The only error in the layout was a very optimistic layout of the ground plane around the oscillator. Leads were short and capacitors were close enough in value. The case of a small surface mounted crystal is not easy to ground. However, during the tests we grounded it with a very short wire without any noticeable change.

Fortunately!
Imagine a world full of BS!
/Janne

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lillahuset wrote:
Maybe this is just proof of how little I know ;^)

/Janne

Don't be shy !
You are encountering one of the hardest tasks there is with these devices.

The other hard task is to make them survive in a heavily polluted (EMC polluted) environment.

I have participated a project where we had this mobile terminal which was an add-on to existing VHF radio. To make it silent enough took us 6 months to complete.

This is so hard because layout really cannot be tested is a breadboard. You have to have near production PCB to see if it works.

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Yes, I know. I used to design boards with DSPs, ECL, ACT and other terrible components. We always used multilayer boards for the ground planes. This product is a two layer board.

The problem with this project is that the boards should cost nothing and do everything. The project is driven by some crazy people that think that just because consumer electronics drop in price every year industrial electronics should also drop in price at least as much.
What they (choose to) fail to understand is that the market for this product is rather small, maybe a few thousand per year so the development cost is a very big part of each unit.

Please, whoever rule this world, take all power away from accountants, marketing people, purchasing people and other lowlife of that kind.

/Janne

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lillahuset wrote:
"Thank you for your replies.

Our conclusion is that we need a new layout.

The most confusing thing is what ccharala noted about the amplitude of the harmonics. In my (previous) world the level of higher harmonics was always lower than the level of higher harmonics. Maybe this is just proof of how little I know ;^)

/Janne"

Me too, was surprised when I discovered this strange spectrum of the "25% duty cycle square wave". This signal is an exeption to what we all are used to.
The furrier analysis theory (at least) says so.

In your design, a distortion of the waveform of the 16Mhz clock oscilator far away the 50% duty cycle, "might" be a reason of your trouble

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ccharala wrote:
lillahuset wrote:
"Thank you for your replies.

Our conclusion is that we need a new layout.

The most confusing thing is what ccharala noted about the amplitude of the harmonics. In my (previous) world the level of higher harmonics was always lower than the level of higher harmonics. Maybe this is just proof of how little I know ;^)

If you look at the spectrum of a signal it is true that the first harmonic is always the highest in amplitude. But when you feed a signal to a circuit that has a frequency dependent impedance (which is any real-life circuit) you are probably going to come across resonance phenomenon. In a radiation measurement you will probably find the strongest harmonics in the spectrum at the places, energy is radiated the most effectively. Changing your board layout might improve this. Try to minimise the current loop area, and trace length. Fill empty places on the PCB with copper and connect these with via's to the ground plane or other high frequency/low impedance system reference. If this still doesn't do the job, you might turn to shielding, but this is quiet expansive.

"Digital is a special case of analog" - George Philbrick