SPI module configuration (CTRL register)

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VinceUK
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Posted by VinceUK: Fri. Jul 1, 2022 - 10:31 AM
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Hi All,

 

I have a query regarding the configuration of the SPI module on the ATXmega128A1U.

 

According to datasheet 8331: bit 6 (ENABLE) of the control register (CTRL) enables the module while bit 4 (MASTER) selects master mode when written to one (see section 22.7.1 CTRL - Control Register). So, if I want to enable a SPI module and configure it as master, both bits shall be set.

 

Could the bits setting order make a difference (i.e. ENABLE before MASTER)? This seems to be relevant for the SPI port C on a particular batch of MCU devices I am using. Basically, the SPI port C, which is enabled, remains as a slave when trying to set it as master. The chip select (SS, PC4) is configured as output and driven high by the software which complies with the datasheet's guidance.

 

I came across the AVR1309 SPI driver source file and both bits are set at the same time, hence my question.
 

Cheers,

Vince

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AVR Microcontrollers, AVR and XMEGA, #ASF #Atmel Studio 7 #driver #SPI, solved, #ATxmega128A1U
Last Edited: Wed. Jul 6, 2022 - 09:51 AM
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Gold Markclawson
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Posted by clawson: Fri. Jul 1, 2022 - 12:57 PM
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Why would you be setting the bits one at a time anyway? Surely you make one write to CTRL setting both bits 4 and 6? 

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N.Winterbottom
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Posted by N.Winterbottom: Sat. Jul 2, 2022 - 11:29 AM
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Bit 4 – MASTER: Master Select
This bit selects master mode when written to one, and slave mode when written to zero. If SS is configured as an
input and driven low while master mode is set, master mode will be cleared.

 Check the order of making SS an output.

 

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VinceUK
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Posted by VinceUK: Mon. Jul 4, 2022 - 08:08 AM (Reply to #2)
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That's a fair point. It's just that I was unable to find any information, except the code example, that confirms a particular way of initializing the SPIC properly.

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Gold Markclawson
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Posted by clawson: Mon. Jul 4, 2022 - 08:46 AM
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Well to answer your hypothetical scenario just think about it. You can only either set enable then master or you can set master then enable. Take the latter (trivial) one first. If you set master first but not enable then nothing really happens because the SPI is not enabled. When you do then set enable it will start in master mode. If you do it the other way round then you will enable first and by default it will start as a slave then just a few opcodes later you will set master and now it will act as master.

 

The only difference between an SPI master and an SPI slave is the action of the clock line. In master mode the SPI drives the clock. If you write something to the data register it will start an eight clock process in which each byte in the data register is presented on MOSI and a pulse will be made on SCK. At the same time the device monitors MISO at each clock period and shifts its 0/1 state into the receive data register. If, on the other hand the device is set to "slave" then the clock line is an input and the device will begin to clock MOSI bits into the receive data register if clock pulses appear on the SCK line. Also writing to the transmit data register will not initiate clocking and transfer.

 

So in the scenario where you start as slave with enable before master. There will be just a very short (few opcode) window during which any activity on SCK might start to clock data into MOSI.

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VinceUK
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Posted by VinceUK: Wed. Jul 6, 2022 - 09:50 AM (Reply to #5)
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Thanks for your detailed explanation. Indeed, the activity on SCK might have caused that. 

 

I confirm that making one write to CTRL setting both bits 4 and 6, as suggested in your previous post, fixed the issue.

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