AVR Freaks

Hi

I can create a steering logic to change the shift register data pin from Circuit 1 to Circuit 2 . However there is also the difference between the output pins order in circuit 1 & 2 .

Circuit 1 output order Q0,Q1,Q2,Q3 (from 1st shift register) Q0,Q1,Q2,Q3 (from 2nd shift register),... and so on

Circuit 2:Output order: Q0,Q0,Q1,Q1,Q2,Q2,Q3,Q3.... and so on (i.q. Q0 form first, Q0 from 2nd etc..)

I hope this was clear???

2 reasons:

1. Difficult to source microcontrollers in the current market, found these logic gates IC easily stocked. Main reason
2. not sure the best way to implement the incoming clock rising pulse to trigger shifting of the bits (by 1 OR by 2) of the PORT output pins? Use external interrupt for clock? Check the Reset Input is high before shifting the bits or do nothing??Just found these logic gates simpler to implement.

I've managed to get the Logic gates IC circuit working (in simulator at least) using two decoders and triggering either/both depending on the mode from a D flip flop. I can include a simulator schematic later if anyone want to look at it.

However, since everyone suggested using a avr, I am trying to create same project on avr. For simulating and testing I've started to work on ATMEGA328p, ideally later i'll port it out on ATTINY when the programmig logic is finalised.

I've also added CLOCK & RESET Outputs so that this can be used to cascade multiple units.

My concept is below:

• CLOCK input (5V nominal): it needs to be min. 1ms long to (needs to be even longer to actuate relay contacts around 5-10ms, but just for advancing channels to select particular relay maybe 1ms is okay). R15 & C7 as low pass filter (cutoff 1.061KHz). Also R15 series resistor provides some protection if the clock is driven when the circuit is powered off?? R17 pulldown resistor to ensure CLK is always LOW. It goes through Schmitt trigger U23 to Uc.
• RESET IN (5V, active HIGH): R16 is pulldown resistor. R15 & C7 low pass filter. RESET needs to be high for the circuit to work for longer time so just increased R16 to 100K with cutoff freq of 160Hz. Again hoping R16 also provides protection if reset is driven when the circuit is powered off??
• SW2 is a dip switch which selects the relay logic mode (1x16 OR 2x8 mode) after the reset is HIGH and the uC is running.It goes through Schmitt trigger U23 to Uc.
• CLK out & RESET Out are cascading outputs (uC C4 & C5 PIN outputs for CLOCK & RESET pin when the relays have clocked through to the end. So the user can add another unit and use these for outputs as CLOCK & RESET inputs for the second unit. Used R13 & R14 as series resistors for protection if they are accidentally driven LOW/HIGH unintentionally. These outputs are cascaded by the Cascade Enable pins through a Schmitt trigger AND gate U23.

Program logic

• when RESET pin is HIGH, uC starts up.
• INT0 is interrupt on rising edge to detect the incoming CLOCK pulse.
• Mode Selector input D3 pin is check to determine the mode (2x8 OR 1x16).
• each CLOCK input pulse increases the counter which advances the relay based on the mode selection.
• Once the last relays have been reached, the next clock advance makes all relays OFF and sends the RESET & CLOCK outputs to he RESET & CLOCK OUT pins for adding another unit if required. Disables the interrupt INT0.
• Whenever the RESET is driven low at the end (or anytime)), everything resets.All relays are OFF. uC is supposed to sleep. I know this just makes the uC enter high impedance state and probably not the best option for minimal current consumption/protected?? Ideas/suggestions?

Below is my code:

#include<avr/io.h>
#include<avr/interrupt.h>
#include<util/delay.h>

volatile int x=0;

unsigned int SNG[16]={0b00000001,0b00000010,0b00010000,0b00100000,0b01000000,0b10000000,0b00000001,0b00000010,0b00000100,0b00001000,0b00010000,0b00100000,0b00000001,0b00000010,0b00000100,0b00001000};
unsigned int DBL[8]={0b00000011,0b00110000,0b11000000,0b00000011,0b00001100,0b00110000,0b00000011,0b00001100};


ISR (INT0_vect)          //External interrupt_zero ISR
{
	//cnt_zero++;
	x=x+1;
  
}


int main()
{
	DDRD=0b11110011;
	DDRB=0b00111111;
	DDRC=0b00111111;
	
		
	EIMSK=0b00000001;	 //enable INT0 INT1 interrupt
	EICRA=0b00000011; //INT0 on rising edge, INT 1 any logical change

	PORTD |= 0b00001000;	//Pull ups on INT 1 (PD3)
	sei();     // Enable global interrupts by setting global interrupt enable bit in SREG
	
	while(1)
	{
		if ((PIND & 0b00001000)==0) 	// Check for switching mode, LOW= 1x16 mode
		{
		switch (x)
		{
			case 1 ... 6:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;				//not sure this is needed to ensure that relays are off before advancing another channel
			PORTD=SNG[x-1];
			break;
			case 7 ... 12:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTB=SNG[x-1];
			break;
			case 13 ... 16:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTC=SNG[x-1];
			break;
			case 17:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTC=0b00110000;		// Enable RESET & CLOCK out
			cli();
			
		}
		}
		else 			// Check for switching mode, HIGH= 2x8 mode
		{
			switch (x)
		{
			case 1 ... 3:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTD=DBL[x-1];
			break;
			case 4 ... 6:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTB=DBL[x-1];
			break;
			case 7 ... 8:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTC=DBL[x-1];
			break;
			case 9:
			PORTB=0x00;
			PORTC=0x00;
			PORTD=0x00;
			PORTC=0b00110000;		// Enable RESET & CLOCK out
			cli();
		}
		}
	}

}

Any ideas/advice is highly appreciated.

Also I am thinking of using protection diodes ( transzorbs) limiting clock & reset & 12V & GND  to 16V as the system will get external 12V inputs and will use a 5V LDO to supply 5V VCC.

mainly due to Low contact resistance for sensitive measurements. I can look into the semiconductor optorelays OR FETs but that's for later, once everything else is sorted.

truckloads indeed..

I am thinking of using a signal relay (something like this).

TXS2SA-L-4.5V-1

eDIT: Its meant to be TXS2SA-4.5V-1

Hi

just wondering if anyone had any improvements ideas/comments on my above approach (circuit &code). Especially:

1. Input/output  CLK & RESET pin protections
2. alternate way to implement RESET while keeping the system responsive enough to detect the change in RESET input (when not connecting it to uC RESET pin)
3. As it stands can i make it so that the RESET input can be higher than 5V ( between 3-8v) ?
4. i am thinking of using internal oscillator. What is the minimum oscillator speed that i can apply in my code to ensure that i can detect and process a 1ms ling clock . I definitely will not be needing to detect anything smaller than 1ms.

sorry for confusions. My idea is the minimum CLOCK pulse width should be no smaller than 1ms long. So, i should be able to at least detect and action (count the advances of relay) on this pulse.
I do not want to use external oscillator as i don’t think its needed for my project( size, cost etc),  also maybe use ATTINY instead of atmega328p. So i was wondering what speed oscillator is needed in my project scenario while  making sure that the executed code is quick enough to work smoothly.

reason for wanting to optimise on oscillator freq. is to try and minimise power drain of the microcontroller as i assume lower freq. oscillator uses lower power??