I'm working with the SAME70 that uses SPI0 to communicate with a graphics processor. The GFX board has a typical sequence of "write a register address, then read or write one or more byte at that address". The key point is that chip select needs to stay asserted across those two steps. However, the GFX library writes the register address with one SPI xfer, and the subsequent data bytes with a second SPI xfer.
This seemed like a perfect use case for the SPI0.CSRn.CSAAT bit. From the documentation:
To facilitate interfacing with [some SPI slave peripherals], the chip select registers [SPI_CSR0...SPI_CSR3] can be programmed with the Chip Select Active After Transfer (CSAAT) bit at 1. This allows the chip select lines to remain in their current state (low = active) until a transfer to another chip select is required. Even if SPI_TDR is not reloaded, the chip select remains active.
But for some reason, NPCS1 is not remaining active between transfers, even though there are no other devices trying to communicate on the SPI bus. Here's the state of SPI.CSR1 just before performing two consecutive transfers:
Here's the code that selects NPCS1 then performs two consecutive transfers:
void write_slice(uint8_t *payload, size_t payload_size) {
unsigned char preamble[] = {0x00, 0x04, 0x80};
SPI0_ChipSelectSetup(SPI_CHIP_SELECT_NPCS1);
SPI0_WriteRead((void *)preamble, sizeof(preamble), NULL, 0);
SPI0_WriteRead((void *)payload, payload_size , NULL, 0);
}And here's the resulting 'scope trace. Top trace is NPCS1 (chip select, low true), subsequent traces are SCK, MISO, MOSI. As you can see, NPCS1 de-asserts between the two transfers:
I cannot see any particular reason that NPCS1 is de-asserting between transfers. Does anyone have experience with this? What am I missing?