SERCOM SPI interrupt enable bit unexpectedly cleared

Log in or register to post comments
Go To Last Post
3 posts / 0 new
Author
Message
jerryr
jerryr's picture
Level: Hangaround
Joined: Fri. Apr 23, 2004
Posts: 405 View posts
Location: Liederbach; Germany
#1
Posted by jerryr: Mon. Jan 10, 2022 - 09:12 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

In a program using a SAMD21 SERCOM as SPI in master mode I have the following code:

SERCOM0->SPI.INTENSET.bit.TXC = 1;
SERCOM0->SPI.INTENCLR.bit.DRE = 1;

At entry the bit DRE is set and TXC is cleared. After the first statement the bits TXC and DRE are set. After the second statement one would expect that only TXC is set, but BOTH bits are cleared.

The problem is fixed by swapping the statements.

The odd behaviour is not described in the SAMD21 Errata document.

Has anyone seen such behaviour?

Thanks for a reply, Jerry

 

The program section is a driver for a MAX7219 8-digit 7 segment LED interface

This topic has a solution.

Tags:

Atmel SMART ARM-based MCUs and MPUs, Atmel Cortex-M MCUs, SERCOM SPI interrupt, solved, #atsamd21, #compiler, atsamd21
Last Edited: Thu. Jan 13, 2022 - 09:35 PM
Top
westfw
westfw's picture
Level: Raving Lunatic
Joined: Wed. Jun 19, 2002
Posts: 5348 View posts
Location: SF Bay area
This reply has been marked as the solution. 
Posted by westfw: Wed. Jan 12, 2022 - 12:33 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1
SERCOM0->SPI.INTENSET.bit.TXC = 1;

Yeah; this has come up before.  Don't use the ".bit." fields when writing to registers where "writing a one clears the bit."  There is no support in ARM for reading individual bits from memory (well, certainly not in SAMD21), so bit fields are implemented by "read the whole word, fiddle with the bitfield, write the whole word."  If reading INTENCLR gives bits that are ones in the positions where interrupts are already enabled, then writing it back will clear all those bits, in addition to the bit you wanted to set.

 

use the .reg. registers and calculate (or find) your own bitmask...

    SERCOM0->SPI.INTENSET.reg = SERCOM_SPI_INTENCLR_TXC;

 

Top
jerryr
jerryr's picture
Level: Hangaround
Joined: Fri. Apr 23, 2004
Posts: 405 View posts
Location: Liederbach; Germany
Posted by jerryr: Thu. Jan 13, 2022 - 09:32 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1

Hello westfw,

   Thanks for the hint. You were right, after replacing the .bit statements with .reg all was well

Best wishes, Jerry

 

Top